Reset cause

General Description

Define RESET_CAUSE mask values.

Macros
#define	CY_SYSLIB_RESET_HWWDT   (0x0001U)
	A basic WatchDog Timer (WDT) reset has occurred since the last power cycle. More...
#define	CY_SYSLIB_RESET_ACT_FAULT   (0x0002U)
	The fault logging system requested a reset from its Active logic. More...
#define	CY_SYSLIB_RESET_DPSLP_FAULT   (0x0004U)
	The fault logging system requested a reset from its Deep-Sleep logic. More...
#define	CY_SYSLIB_RESET_SOFT   (0x0010U)
	The CPU requested a system reset through it's SYSRESETREQ. More...
#define	CY_SYSLIB_RESET_SWWDT0   (0x0020U)
	The Multi-Counter Watchdog timer #0 reset has occurred since the last power cycle. More...
#define	CY_SYSLIB_RESET_SWWDT1   (0x0040U)
	The Multi-Counter Watchdog timer #1 reset has occurred since the last power cycle. More...
#define	CY_SYSLIB_RESET_SWWDT2   (0x0080U)
	The Multi-Counter Watchdog timer #2 reset has occurred since the last power cycle. More...
#define	CY_SYSLIB_RESET_SWWDT3   (0x0100U)
	The Multi-Counter Watchdog timer #3 reset has occurred since the last power cycle. More...
#define	CY_SYSLIB_RESET_HIB_WAKEUP   (0x40000UL)
	The reset has occurred on a wakeup from Hibernate power mode. More...

Macro Definition Documentation

CY_SYSLIB_RESET_HWWDT

#define CY_SYSLIB_RESET_HWWDT   (0x0001U)

A basic WatchDog Timer (WDT) reset has occurred since the last power cycle.

CY_SYSLIB_RESET_ACT_FAULT

#define CY_SYSLIB_RESET_ACT_FAULT   (0x0002U)

The fault logging system requested a reset from its Active logic.

CY_SYSLIB_RESET_DPSLP_FAULT

#define CY_SYSLIB_RESET_DPSLP_FAULT   (0x0004U)

The fault logging system requested a reset from its Deep-Sleep logic.

CY_SYSLIB_RESET_SOFT

#define CY_SYSLIB_RESET_SOFT   (0x0010U)

The CPU requested a system reset through it's SYSRESETREQ.

This can be done via a debugger probe or in firmware.

CY_SYSLIB_RESET_SWWDT0

#define CY_SYSLIB_RESET_SWWDT0   (0x0020U)

The Multi-Counter Watchdog timer #0 reset has occurred since the last power cycle.

CY_SYSLIB_RESET_SWWDT1

#define CY_SYSLIB_RESET_SWWDT1   (0x0040U)

The Multi-Counter Watchdog timer #1 reset has occurred since the last power cycle.

CY_SYSLIB_RESET_SWWDT2

#define CY_SYSLIB_RESET_SWWDT2   (0x0080U)

The Multi-Counter Watchdog timer #2 reset has occurred since the last power cycle.

CY_SYSLIB_RESET_SWWDT3

#define CY_SYSLIB_RESET_SWWDT3   (0x0100U)

The Multi-Counter Watchdog timer #3 reset has occurred since the last power cycle.

CY_SYSLIB_RESET_HIB_WAKEUP

#define CY_SYSLIB_RESET_HIB_WAKEUP   (0x40000UL)

The reset has occurred on a wakeup from Hibernate power mode.