Interrupt Masks

General Description

Macros
#define	CY_DMAC_INTR_COMPLETION   (DMAC_CH_V2_INTR_COMPLETION_Msk)
	Bit 0: Completion of data transfer(s) as specified by the descriptor's interruptType setting. More...
#define	CY_DMAC_INTR_SRC_BUS_ERROR   (DMAC_CH_V2_INTR_SRC_BUS_ERROR_Msk)
	Bit 1: Bus error for a load from the source. More...
#define	CY_DMAC_INTR_DST_BUS_ERROR   (DMAC_CH_V2_INTR_DST_BUS_ERROR_Msk)
	Bit 2: Bus error for a store to the destination. More...
#define	CY_DMAC_INTR_SRC_MISAL   (DMAC_CH_V2_INTR_SRC_MISAL_Msk)
	Bit 3: Misalignment of the source address. More...
#define	CY_DMAC_INTR_DST_MISAL   (DMAC_CH_V2_INTR_DST_MISAL_Msk)
	Bit 4: Misalignment of the destination address. More...
#define	CY_DMAC_INTR_CURR_PTR_NULL   (DMAC_CH_V2_INTR_CURR_PTR_NULL_Msk)
	Bit 5: The channel is enabled and the current descriptor pointer is "0". More...
#define	CY_DMAC_INTR_ACTIVE_CH_DISABLED   (DMAC_CH_V2_INTR_ACTIVE_CH_DISABLED_Msk)
	Bit 6: The channel is disabled and the data transfer engine is busy. More...
#define	CY_DMAC_INTR_DESCR_BUS_ERROR   (DMAC_CH_V2_INTR_DESCR_BUS_ERROR_Msk)
	Bit 7: Bus error for a load of the descriptor. More...

Macro Definition Documentation

CY_DMAC_INTR_COMPLETION

#define CY_DMAC_INTR_COMPLETION   (DMAC_CH_V2_INTR_COMPLETION_Msk)

Bit 0: Completion of data transfer(s) as specified by the descriptor's interruptType setting.

CY_DMAC_INTR_SRC_BUS_ERROR

#define CY_DMAC_INTR_SRC_BUS_ERROR   (DMAC_CH_V2_INTR_SRC_BUS_ERROR_Msk)

Bit 1: Bus error for a load from the source.

CY_DMAC_INTR_DST_BUS_ERROR

#define CY_DMAC_INTR_DST_BUS_ERROR   (DMAC_CH_V2_INTR_DST_BUS_ERROR_Msk)

Bit 2: Bus error for a store to the destination.

CY_DMAC_INTR_SRC_MISAL

#define CY_DMAC_INTR_SRC_MISAL   (DMAC_CH_V2_INTR_SRC_MISAL_Msk)

Bit 3: Misalignment of the source address.

CY_DMAC_INTR_DST_MISAL

#define CY_DMAC_INTR_DST_MISAL   (DMAC_CH_V2_INTR_DST_MISAL_Msk)

Bit 4: Misalignment of the destination address.

CY_DMAC_INTR_CURR_PTR_NULL

#define CY_DMAC_INTR_CURR_PTR_NULL   (DMAC_CH_V2_INTR_CURR_PTR_NULL_Msk)

Bit 5: The channel is enabled and the current descriptor pointer is "0".

CY_DMAC_INTR_ACTIVE_CH_DISABLED

#define CY_DMAC_INTR_ACTIVE_CH_DISABLED   (DMAC_CH_V2_INTR_ACTIVE_CH_DISABLED_Msk)

Bit 6: The channel is disabled and the data transfer engine is busy.

CY_DMAC_INTR_DESCR_BUS_ERROR

#define CY_DMAC_INTR_DESCR_BUS_ERROR   (DMAC_CH_V2_INTR_DESCR_BUS_ERROR_Msk)

Bit 7: Bus error for a load of the descriptor.