PSoC 6 Peripheral Driver Library
DMAC (Direct Memory Access Controller)

General Description

Configures the DMA Controller block, channels and descriptors.

The functions and other declarations used in this driver are in cy_dmac.h. You can include cy_pdl.h to get access to all functions and declarations in the PDL.

The DMA Controller channel can be used in any project to transfer data without CPU intervention basing on a hardware trigger signal from another component.

The DMA Controller block has a set of registers, a base hardware address, and supports multiple channels. Many API functions for the DMAC driver require a base hardware address and channel number. Ensure that you use the correct hardware address for the DMA Controller block in use.


Configuration Considerations

To set up a DMAC driver, initialize a descriptor, initialize and enable a channel, and enable the DMAC block.

To set up a descriptor, provide the configuration parameters for the descriptor in the cy_stc_dmac_descriptor_config_t structure. Then call the Cy_DMAC_Descriptor_Init function to initialize the descriptor in SRAM. You can modify the source and destination addresses dynamically by calling Cy_DMAC_Descriptor_SetSrcAddress and Cy_DMAC_Descriptor_SetDstAddress.

To set up a DMAC channel, provide a filled cy_stc_dmac_channel_config_t structure. Call the Cy_DMAC_Channel_Init function, specifying the channel number. Use Cy_DMAC_Channel_Enable to enable the configured DMAC channel.

Call Cy_DMAC_Channel_Enable for each DMAC channel in use.

When configured, another peripheral typically triggers the DMAC channel. The trigger is connected to the DMAC channel using the trigger multiplexer. The trigger multiplexer driver has a software trigger you can use in firmware to trigger the DMAC channel. See the Trigger Multiplexer documentation.

The following is a simplified structure of the DMAC driver API interdependencies in a typical user application:


NOTE: Even if a DMAC channel is enabled, it is not operational until the DMAC block is enabled using function Cy_DMAC_Enable.
NOTE: If the DMAC descriptor is configured to generate an interrupt, the interrupt must be enabled using the Cy_DMAC_Channel_SetInterruptMask function for each DMAC channel.

For example:

/* Scenario: Initialize a 1D descriptor */
#define DATACNT (8UL)
cy_stc_dmac_descriptor_t nextDescriptor;
uint32_t src[DATACNT];
uint32_t dst[DATACNT];
.interruptType = CY_DMAC_DESCR,
.triggerOutType = CY_DMAC_DESCR,
.triggerInType = CY_DMAC_DESCR,
.dataSize = CY_DMAC_WORD,
.descriptorType = CY_DMAC_1D_TRANSFER,
.srcAddress = &src,
.dstAddress = &dst,
.srcXincrement = 1U,
.dstXincrement = 1U,
.xCount = DATACNT,
.srcYincrement = 0U,
.dstYincrement = 0U,
.yCount = 1UL,
.nextDescriptor = &nextDescriptor,
if (CY_DMAC_SUCCESS != Cy_DMAC_Descriptor_Init(&descriptor, &descriptor_cfg))
/* Insert error handling */
/* Scenario: Setup and enable the DMAC channel 0 */
channelConfig.enable = false;
channelConfig.bufferable = false;
if (CY_DMAC_SUCCESS != Cy_DMAC_Channel_Init(DMAC, 0UL, &channelConfig))
/* Insert error handling */
Cy_DMAC_Channel_SetDescriptor(DMAC, 0UL, &descriptor);
Cy_DMAC_Channel_SetPriority(DMAC, 0UL, 3UL);

More Information.

See the DMAC chapter of the device technical reference manual (TRM).

MISRA-C Compliance

The DMAC driver has the following specific deviations:

MISRA Rule Rule Class (Required/Advisory) Rule Description Description of Deviation(s)
10.3 R A composite expression of the "essentially unsigned" type is being cast to a different type category. The value got from the bitfield physically cannot exceed the enumeration that describes this bitfield. So, the code is safe by design.
11.4 A A cast should not be performed between a pointer to object type and a different pointer to object type. The cast to another type is made intentionally for better code readability.


VersionChangesReason for Change
1.10.1 Minor documentation updates. Documentation enhancement.
1.10 The Cy_DMAC_Channel_ClearInterrupt is changed. Minor defect fixing.
1.0 The initial version.

API Reference

 Interrupt Masks
 Data Structures
 Enumerated Types