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CAT2 Peripheral Driver Library
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CAT2 Peripheral Driver Library
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Configure the selected Analog Channel.
Data Fields | |
| cy_en_dsadc_achan_aaf_cutoff_freq_t | aafCutoffFreq |
| Select the anti-aliasing filter cut-off frequency. More... | |
| cy_en_dsadc_achan_circuit_chopping_t | aafDisconnectCount |
| Set the cycle that disconnects the AAF for the set number of clock cycles after a Fchop clock edge. | |
| cy_en_dsadc_buffer_power_level_t | bufferPowerLevel |
| Set the buffer Power Levels. More... | |
| cy_en_dsadc_achan_modulator_comp_power_t | compPower |
| Select the chopping clock frequency. More... | |
| cy_en_dsadc_chopping_clock_divider_t | datapathChoppingDivider |
| Set the power control for the quantizer block. More... | |
| cy_en_dsadc_dem_mode_t | demMode |
| Set the dynamic element matching (DEM) mode. More... | |
| cy_en_dsadc_achan_modulator_first_stage_power_t | firstStagePower |
| Select the First stage Opamp power level. More... | |
| cy_en_dsadc_chopping_clock_divider_t | modulatorChoppingDivider |
| Select the modulator chopping clock frequency. More... | |
| cy_en_dsadc_achan_modulator_non_overlap_delay_t | nonOverlapDelay |
| Select the Non-Overlap delay of clock phases. More... | |
| cy_en_dsadc_pga_power_level_t | pgaPowerLevel |
| Select the PGA power level. More... | |
| cy_en_dsadc_achan_trigger_t | primaryTrigger |
| Select the primary trigger source for the ACHAN. | |
| cy_en_dsadc_achan_trigger_t | secondaryTrigger |
| Select the secondary trigger source for the ACHAN. | |
| cy_en_dsadc_achan_modulator_second_third_stage_power_t | secondThirdStagePower |
| Select the power level for the second and third integrator stages. | |
| cy_en_dsadc_achan_modulator_summer_power_t | summerPower |
| Select the power level for the summer block. More... | |
| cy_en_dsadc_achan_trigger_synchronized_t | syncPrimaryTrigger |
| Enable to synchronize the trigger signal to the delta-sigma modulator (DSM) clock domain, or bypass clock domain synchronization of the trigger signal. | |
| cy_en_dsadc_achan_trigger_synchronized_t | syncSecondaryTrigger |
| Enable to synchronize the trigger signal to the DSM clock domain, or bypass clock domain synchronization of the trigger signal. | |
| cy_en_dsadc_achan_pump_clock_source_t | pumpClock |
| The pump clock frequency is set based off the source clock frequency. More... | |
| cy_en_dsadc_achan_reference_vcm_power_level_t | vcmPowerLevel |
| Select the power level for the voltage reference buffer. More... | |
| cy_en_dsadc_achan_reference_vref_power_level_t | vrefPower |
| Select the positive pump power level. More... | |
| uint8_t | overloadDetectThr |
| Set the overload detect threshold. More... | |
| bool | enableDem |
| Enable or disable dynamic element matching (DEM). More... | |
| bool | enableReset1 |
| Enable or disable 1st stage integrating capacitance to be reset. More... | |
| bool | enableReset2 |
| Enable or disable 2nd stage integrating capacitance to be reset. More... | |
| bool | enableReset3 |
| Enable or disable 3rd stage integrating capacitance to be reset. More... | |
| bool | enableSecIntegrChopping |
| Enable or disable the 2nd stage circuit chopping. More... | |
| bool | useOverloadDetection |
| Enable / Configure the overload detection circuitry. More... | |
| cy_en_dsadc_achan_aaf_cutoff_freq_t cy_stc_dsadc_achan_config_t::aafCutoffFreq |
Select the anti-aliasing filter cut-off frequency.
| cy_en_dsadc_buffer_power_level_t cy_stc_dsadc_achan_config_t::bufferPowerLevel |
Set the buffer Power Levels.
| cy_en_dsadc_achan_modulator_comp_power_t cy_stc_dsadc_achan_config_t::compPower |
Select the chopping clock frequency.
| cy_en_dsadc_chopping_clock_divider_t cy_stc_dsadc_achan_config_t::datapathChoppingDivider |
Set the power control for the quantizer block.
| cy_en_dsadc_dem_mode_t cy_stc_dsadc_achan_config_t::demMode |
Set the dynamic element matching (DEM) mode.
| cy_en_dsadc_achan_modulator_first_stage_power_t cy_stc_dsadc_achan_config_t::firstStagePower |
Select the First stage Opamp power level.
| cy_en_dsadc_chopping_clock_divider_t cy_stc_dsadc_achan_config_t::modulatorChoppingDivider |
Select the modulator chopping clock frequency.
| cy_en_dsadc_achan_modulator_non_overlap_delay_t cy_stc_dsadc_achan_config_t::nonOverlapDelay |
Select the Non-Overlap delay of clock phases.
| cy_en_dsadc_pga_power_level_t cy_stc_dsadc_achan_config_t::pgaPowerLevel |
Select the PGA power level.
| cy_en_dsadc_achan_modulator_summer_power_t cy_stc_dsadc_achan_config_t::summerPower |
Select the power level for the summer block.
| cy_en_dsadc_achan_pump_clock_source_t cy_stc_dsadc_achan_config_t::pumpClock |
The pump clock frequency is set based off the source clock frequency.
If the source clock frequency is 48 MHz, then this should be CY_DSADC_ACHAN_PUMP_CLOCK_SOURCE_48MHZ. If the source clock frequency is 24 MHz, then this should be set to CY_DSADC_ACHAN_PUMP_CLOCK_SOURCE_24MHZ. These are the only two valid source clock frequencies for the ADC.
| cy_en_dsadc_achan_reference_vcm_power_level_t cy_stc_dsadc_achan_config_t::vcmPowerLevel |
Select the power level for the voltage reference buffer.
| cy_en_dsadc_achan_reference_vref_power_level_t cy_stc_dsadc_achan_config_t::vrefPower |
Select the positive pump power level.
| uint8_t cy_stc_dsadc_achan_config_t::overloadDetectThr |
Set the overload detect threshold.
| bool cy_stc_dsadc_achan_config_t::enableDem |
Enable or disable dynamic element matching (DEM).
| bool cy_stc_dsadc_achan_config_t::enableReset1 |
Enable or disable 1st stage integrating capacitance to be reset.
| bool cy_stc_dsadc_achan_config_t::enableReset2 |
Enable or disable 2nd stage integrating capacitance to be reset.
| bool cy_stc_dsadc_achan_config_t::enableReset3 |
Enable or disable 3rd stage integrating capacitance to be reset.
| bool cy_stc_dsadc_achan_config_t::enableSecIntegrChopping |
Enable or disable the 2nd stage circuit chopping.
| bool cy_stc_dsadc_achan_config_t::useOverloadDetection |
Enable / Configure the overload detection circuitry.
Overload detection can be useful to avoid input saturation. It is recommended to disable overload detection (set this to 'false') while debugging the ADC. Enable overload detection (set this to 'true') is recommended for the final project implementation.