ACHAN Enumerated Types

Enumerations
enum	cy_en_dsadc_achan_circuit_chopping_t {   CY_DSADC_ACHAN_CIRCUIT_CHOPPING_OFF = 0U,   CY_DSADC_ACHAN_CIRCUIT_CHOPPING_CYCLE_1 = 1U,   CY_DSADC_ACHAN_CIRCUIT_CHOPPING_CYCLE_2 = 2U,   CY_DSADC_ACHAN_CIRCUIT_CHOPPING_CYCLE_4 = 3U }
	Configure the circuit chopping. More...
enum	cy_en_dsadc_buffer_power_level_t {   CY_DSADC_BUFFER_POWER_LEVEL_32_PERCENT = 0U,   CY_DSADC_BUFFER_POWER_LEVEL_55_PERCENT = 1U,   CY_DSADC_BUFFER_POWER_LEVEL_78_PERCENT = 2U,   CY_DSADC_BUFFER_POWER_LEVEL_100_PERCENT = 3U }
	Power level for the buffer before the modulator. More...
enum	cy_en_dsadc_achan_modulator_comp_power_t {   CY_DSADC_ACHAN_MODULATOR_COMP_POWER_50 = 0U,   CY_DSADC_ACHAN_MODULATOR_COMP_POWER_75 = 1U,   CY_DSADC_ACHAN_MODULATOR_COMP_POWER_100 = 2U,   CY_DSADC_ACHAN_MODULATOR_COMP_POWER_200 = 3U }
	Configure the power setting of the quantizer block. More...
enum	cy_en_dsadc_achan_modulator_first_stage_power_t {   CY_DSADC_ACHAN_MODULATOR_FIRST_STAGE_POWER_10 = 0U,   CY_DSADC_ACHAN_MODULATOR_FIRST_STAGE_POWER_31 = 1U,   CY_DSADC_ACHAN_MODULATOR_FIRST_STAGE_POWER_44 = 2U,   CY_DSADC_ACHAN_MODULATOR_FIRST_STAGE_POWER_63 = 3U,   CY_DSADC_ACHAN_MODULATOR_FIRST_STAGE_POWER_75 = 4U,   CY_DSADC_ACHAN_MODULATOR_FIRST_STAGE_POWER_88 = 5U,   CY_DSADC_ACHAN_MODULATOR_FIRST_STAGE_POWER_100 = 6U,   CY_DSADC_ACHAN_MODULATOR_FIRST_STAGE_POWER_150 = 7U }
	Configure the PGA Gain for Gain Level Structure. More...
enum	cy_en_dsadc_achan_modulator_non_overlap_delay_t {   CY_DSADC_ACHAN_MODULATOR_NON_OVERLAP_DELAY_LOW = 0U,   CY_DSADC_ACHAN_MODULATOR_NON_OVERLAP_DELAY_MEDIUM = 1U,   CY_DSADC_ACHAN_MODULATOR_NON_OVERLAP_DELAY_HIGH = 2U,   CY_DSADC_ACHAN_MODULATOR_NON_OVERLAP_DELAY_VERY_HIGH = 3U }
	Configure the Non-overlap delay of the modulator clock phases. More...
enum	cy_en_dsadc_achan_modulator_second_third_stage_power_t {   CY_DSADC_ACHAN_MODULATOR_SECOND_THIRD_STAGE_POWER_75 = 0U,   CY_DSADC_ACHAN_MODULATOR_SECOND_THIRD_STAGE_POWER_81 = 1U,   CY_DSADC_ACHAN_MODULATOR_SECOND_THIRD_STAGE_POWER_94 = 2U,   CY_DSADC_ACHAN_MODULATOR_SECOND_THIRD_STAGE_POWER_100 = 3U,   CY_DSADC_ACHAN_MODULATOR_SECOND_THIRD_STAGE_POWER_150 = 4U }
	Configure the Second and Third Opamp Power Structure. More...
enum	cy_en_dsadc_achan_modulator_summer_power_t {   CY_DSADC_ACHAN_MODULATOR_SUMMER_POWER_75 = 0U,   CY_DSADC_ACHAN_MODULATOR_SUMMER_POWER_81 = 1U,   CY_DSADC_ACHAN_MODULATOR_SUMMER_POWER_94 = 2U,   CY_DSADC_ACHAN_MODULATOR_SUMMER_POWER_100 = 3U,   CY_DSADC_ACHAN_MODULATOR_SUMMER_POWER_150 = 4U }
	Configure the Summer Power Structure. More...
enum	cy_en_dsadc_achan_pump_clock_source_t {   CY_DSADC_ACHAN_PUMP_CLOCK_SOURCE_48MHZ = 0U,   CY_DSADC_ACHAN_PUMP_CLOCK_SOURCE_24MHZ = 1U,   CY_DSADC_ACHAN_PUMP_CLOCK_SOURCE_HFCLK_48MHZ = 2U,   CY_DSADC_ACHAN_PUMP_CLOCK_SOURCE_HFCLK_24MHZ = 3U }
	Configure the Analog Channel Pump clock divider based on the source clock frequency. More...
enum	cy_en_dsadc_achan_trigger_t {   CY_DSADC_ACHAN_TRIGGER_HW_IN0 = 0U,   CY_DSADC_ACHAN_TRIGGER_HW_IN1 = 1U,   CY_DSADC_ACHAN_TRIGGER_HW_IN2 = 2U,   CY_DSADC_ACHAN_TRIGGER_HW_IN3 = 3U,   CY_DSADC_ACHAN_TRIGGER_FW = 4U }
	Select the Primary or Secondary Trigger source. More...
enum	cy_en_dsadc_achan_reference_vcm_power_level_t {   CY_DSADC_VCM_POWER_LEVEL_LOW = 0U,   CY_DSADC_VCM_POWER_LEVEL_MED = 1U,   CY_DSADC_VCM_POWER_LEVEL_HIGH = 2U,   CY_DSADC_VCM_POWER_LEVEL_TURBO = 3U }
	Configure the positive pump's power level. More...
enum	cy_en_dsadc_achan_reference_vref_power_level_t {   CY_DSADC_VREF_POWER_LEVEL_LOW = 0U,   CY_DSADC_VREF_POWER_LEVEL_MED = 1U,   CY_DSADC_VREF_POWER_LEVEL_HIGH = 2U,   CY_DSADC_VREF_POWER_LEVEL_TURBO = 3U }
	Configure the positive pump's power level. More...
enum	cy_en_dsadc_achan_trigger_synchronized_t {   CY_DSADC_ACHAN_TRIGGER_UNSYNCHRONIZED = 0U,   CY_DSADC_ACHAN_TRIGGER_SYNCHRONIZED = 1U }
	Configure the trigger synchronization. More...
enum	cy_en_dsadc_dem_mode_t {   CY_DSADC_DEM_MODE_DWA = 0U,   CY_DSADC_DEM_MODE_ADWA = 1U,   CY_DSADC_DEM_MODE_BIDWA = 2U }
	The mode of dynamic element matching based dynamic element matching (DEM) scheme. More...
enum	cy_en_dsadc_pga_power_level_t {   CY_DSADC_PGA_POWER_LEVEL_39_PERCENT = 0U,   CY_DSADC_PGA_POWER_LEVEL_58_PERCENT = 1U,   CY_DSADC_PGA_POWER_LEVEL_78_PERCENT = 2U,   CY_DSADC_PGA_POWER_LEVEL_100_PERCENT = 3U }
	The power of the programmable gain amplifier (PGA). More...
enum	cy_en_dsadc_achan_aaf_cutoff_freq_t {   CY_DSADC_ACHAN_AAF_CUTOFF_FREQ_30KHZ = 0U,   CY_DSADC_ACHAN_AAF_CUTOFF_FREQ_10KHZ = 1U,   CY_DSADC_ACHAN_AAF_CUTOFF_FREQ_20KHZ = 2U }
	Anti-Aliasing Filter (AAF) Cut-off Frequency. More...
enum	cy_en_dsadc_achan_chopping_type_t {   CY_DSADC_ACHAN_CHOPPING_OFF = 0U,   CY_DSADC_ACHAN_CHOPPING_CHANNEL = 1U,   CY_DSADC_ACHAN_CHOPPING_CROSS = 3U }
	Configure the channel chopping type. More...
enum	cy_en_dsadc_achan0_2temp_trim_gain_type_t {   CY_DSADC_ACHAN0_2TEMP_GAIN_1X = 0U,   CY_DSADC_ACHAN0_2TEMP_GAIN_2X = 1U,   CY_DSADC_ACHAN0_2TEMP_GAIN_4X = 2U,   CY_DSADC_ACHAN0_2TEMP_GAIN_8X = 3U,   CY_DSADC_ACHAN0_2TEMP_GAIN_16X = 4U,   CY_DSADC_ACHAN0_2TEMP_GAIN_32X = 5U,   CY_DSADC_ACHAN0_2TEMP_GAIN_64X = 6U,   CY_DSADC_ACHAN0_2TEMP_GAIN_128X = 7U,   CY_DSADC_ACHAN0_2TEMP_GAIN_256X = 8U,   CY_DSADC_ACHAN0_2TEMP_GAIN_512X = 9U }
	The gain value to refer to the two temperature trim values for ACHAN0. More...
enum	cy_en_dsadc_achan1_2temp_trim_gain_type_t {   CY_DSADC_ACHAN1_2TEMP_GAIN_0P5X = 0U,   CY_DSADC_ACHAN1_2TEMP_GAIN_1X = 1U,   CY_DSADC_ACHAN1_2TEMP_GAIN_2X = 2U,   CY_DSADC_ACHAN1_2TEMP_GAIN_4X = 3U,   CY_DSADC_ACHAN1_2TEMP_GAIN_8X = 4U,   CY_DSADC_ACHAN1_2TEMP_GAIN_16X = 5U,   CY_DSADC_ACHAN1_2TEMP_GAIN_32X = 6U,   CY_DSADC_ACHAN1_2TEMP_GAIN_64X = 7U,   CY_DSADC_ACHAN1_2TEMP_GAIN_128X = 8U,   CY_DSADC_ACHAN1_2TEMP_GAIN_256X = 9U,   CY_DSADC_ACHAN1_2TEMP_GAIN_512X = 10U }
	The gain value to refer to the two temperature trim values for ACHAN1. More...
enum	cy_en_dsadc_achan_3temp_trim_divider_type_t {   CY_DSADC_ACHAN_3TEMP_VSENSE_16 = 0U,   CY_DSADC_ACHAN_3TEMP_VSENSE_24 = 1U,   CY_DSADC_ACHAN_3TEMP_VDIAG_16 = 2U,   CY_DSADC_ACHAN_3TEMP_VDIAG_24 = 3U }
	The divider output value to refer to the three temperature trim values for ACHAN. More...

Detailed Description

Enumeration Type Documentation

cy_en_dsadc_achan_circuit_chopping_t

enum cy_en_dsadc_achan_circuit_chopping_t

Configure the circuit chopping.

Enumerator
CY_DSADC_ACHAN_CIRCUIT_CHOPPING_OFF	Circuit chopping off.
CY_DSADC_ACHAN_CIRCUIT_CHOPPING_CYCLE_1	Disconnect Anti-Aliasing Filter (AAF) (SW1 see aaf) for 1 Delta-Sigma Modulator (DSM) clock cycle after Fchop clock edge.
CY_DSADC_ACHAN_CIRCUIT_CHOPPING_CYCLE_2	Disconnect Anti-Aliasing Filter (AAF) (SW1 see aaf) for 2 Delta-Sigma Modulator (DSM) clock cycle after Fchop clock edge.
CY_DSADC_ACHAN_CIRCUIT_CHOPPING_CYCLE_4	Disconnect Anti-Aliasing Filter (AAF) (SW1 see aaf) for 4 Delta-Sigma Modulator (DSM) clock cycle after Fchop clock edge.

cy_en_dsadc_buffer_power_level_t

enum cy_en_dsadc_buffer_power_level_t

Power level for the buffer before the modulator.

Enumerator
CY_DSADC_BUFFER_POWER_LEVEL_32_PERCENT	Approximately 32% power.
CY_DSADC_BUFFER_POWER_LEVEL_55_PERCENT	Approximately 55% power.
CY_DSADC_BUFFER_POWER_LEVEL_78_PERCENT	Approximately 78% power.
CY_DSADC_BUFFER_POWER_LEVEL_100_PERCENT	Full power.

cy_en_dsadc_achan_modulator_comp_power_t

enum cy_en_dsadc_achan_modulator_comp_power_t

Configure the power setting of the quantizer block.

Enumerator
CY_DSADC_ACHAN_MODULATOR_COMP_POWER_50	Quantizer power setting (50%)
CY_DSADC_ACHAN_MODULATOR_COMP_POWER_75	Quantizer power setting (75%)
CY_DSADC_ACHAN_MODULATOR_COMP_POWER_100	Quantizer power setting (100%)
CY_DSADC_ACHAN_MODULATOR_COMP_POWER_200	Quantizer power setting (200%)

cy_en_dsadc_achan_modulator_first_stage_power_t

enum cy_en_dsadc_achan_modulator_first_stage_power_t

Configure the PGA Gain for Gain Level Structure.

The recommended power setting for performance is the "100%" setting

Enumerator
CY_DSADC_ACHAN_MODULATOR_FIRST_STAGE_POWER_10	Power setting for first stage Opamp power (10%)
CY_DSADC_ACHAN_MODULATOR_FIRST_STAGE_POWER_31	Power setting for first stage Opamp power (31%)
CY_DSADC_ACHAN_MODULATOR_FIRST_STAGE_POWER_44	Power setting for first stage Opamp power (44%)
CY_DSADC_ACHAN_MODULATOR_FIRST_STAGE_POWER_63	Power setting for first stage Opamp power (63%)
CY_DSADC_ACHAN_MODULATOR_FIRST_STAGE_POWER_75	Power setting for first stage Opamp power (75%)
CY_DSADC_ACHAN_MODULATOR_FIRST_STAGE_POWER_88	Power setting for first stage Opamp power (88%)
CY_DSADC_ACHAN_MODULATOR_FIRST_STAGE_POWER_100	Power setting for first stage Opamp power (100%)
CY_DSADC_ACHAN_MODULATOR_FIRST_STAGE_POWER_150	Power setting for first stage Opamp power (150%)

cy_en_dsadc_achan_modulator_non_overlap_delay_t

enum cy_en_dsadc_achan_modulator_non_overlap_delay_t

Configure the Non-overlap delay of the modulator clock phases.

Enumerator
CY_DSADC_ACHAN_MODULATOR_NON_OVERLAP_DELAY_LOW	1.57 ns typical delay.
CY_DSADC_ACHAN_MODULATOR_NON_OVERLAP_DELAY_MEDIUM	2.54 ns typical delay.
CY_DSADC_ACHAN_MODULATOR_NON_OVERLAP_DELAY_HIGH	6.47 ns typical delay.
CY_DSADC_ACHAN_MODULATOR_NON_OVERLAP_DELAY_VERY_HIGH	9.91 ns typical delay.

cy_en_dsadc_achan_modulator_second_third_stage_power_t

enum cy_en_dsadc_achan_modulator_second_third_stage_power_t

Configure the Second and Third Opamp Power Structure.

Enumerator
CY_DSADC_ACHAN_MODULATOR_SECOND_THIRD_STAGE_POWER_75	Power setting for second and third stage Opamp power (75%)
CY_DSADC_ACHAN_MODULATOR_SECOND_THIRD_STAGE_POWER_81	Power setting for second and third stage Opamp power (81%)
CY_DSADC_ACHAN_MODULATOR_SECOND_THIRD_STAGE_POWER_94	Power setting for second and third stage Opamp power (94%)
CY_DSADC_ACHAN_MODULATOR_SECOND_THIRD_STAGE_POWER_100	Power setting for second and third stage Opamp power (100%)
CY_DSADC_ACHAN_MODULATOR_SECOND_THIRD_STAGE_POWER_150	Power setting for second and third stage Opamp power (150%)

cy_en_dsadc_achan_modulator_summer_power_t

enum cy_en_dsadc_achan_modulator_summer_power_t

Configure the Summer Power Structure.

Enumerator
CY_DSADC_ACHAN_MODULATOR_SUMMER_POWER_75	Summer power setting (75%)
CY_DSADC_ACHAN_MODULATOR_SUMMER_POWER_81	Summer power setting (81%)
CY_DSADC_ACHAN_MODULATOR_SUMMER_POWER_94	Summer power setting (94%)
CY_DSADC_ACHAN_MODULATOR_SUMMER_POWER_100	Summer power setting (100%)
CY_DSADC_ACHAN_MODULATOR_SUMMER_POWER_150	Summer power setting (150%)

cy_en_dsadc_achan_pump_clock_source_t

enum cy_en_dsadc_achan_pump_clock_source_t

Configure the Analog Channel Pump clock divider based on the source clock frequency.

Enumerator
CY_DSADC_ACHAN_PUMP_CLOCK_SOURCE_48MHZ	Source clock is 48 MHz, and is sourced by the Pump Clock in the ACHAN.
CY_DSADC_ACHAN_PUMP_CLOCK_SOURCE_24MHZ	Source clock is 24 MHz, and is sourced by the Pump Clock in the ACHAN.
CY_DSADC_ACHAN_PUMP_CLOCK_SOURCE_HFCLK_48MHZ	Source clock is 48 MHz, and is sourced by the High-Frequency Clock (HFCLK)
CY_DSADC_ACHAN_PUMP_CLOCK_SOURCE_HFCLK_24MHZ	Source clock is 24 MHz, and is sourced by the High-Frequency Clock (HFCLK)

cy_en_dsadc_achan_trigger_t

enum cy_en_dsadc_achan_trigger_t

Select the Primary or Secondary Trigger source.

Enumerator
CY_DSADC_ACHAN_TRIGGER_HW_IN0	Maps to Hardware IN0 - This does not disable firmware triggering.
CY_DSADC_ACHAN_TRIGGER_HW_IN1	Maps to Hardware IN1 - This does not disable firmware triggering.
CY_DSADC_ACHAN_TRIGGER_HW_IN2	Maps to Hardware IN2 - This does not disable firmware triggering.
CY_DSADC_ACHAN_TRIGGER_HW_IN3	Maps to Hardware IN3 - This does not disable firmware triggering.
CY_DSADC_ACHAN_TRIGGER_FW	Use Firmware triggering only - Disable hardware triggering of the selected trigger source (primary / secondary)

cy_en_dsadc_achan_reference_vcm_power_level_t

enum cy_en_dsadc_achan_reference_vcm_power_level_t

Configure the positive pump's power level.

Enumerator
CY_DSADC_VCM_POWER_LEVEL_LOW	Low power.
CY_DSADC_VCM_POWER_LEVEL_MED	Medium power.
CY_DSADC_VCM_POWER_LEVEL_HIGH	High power.
CY_DSADC_VCM_POWER_LEVEL_TURBO	Turbo power.

cy_en_dsadc_achan_reference_vref_power_level_t

enum cy_en_dsadc_achan_reference_vref_power_level_t

Configure the positive pump's power level.

Enumerator
CY_DSADC_VREF_POWER_LEVEL_LOW	Low power.
CY_DSADC_VREF_POWER_LEVEL_MED	Medium power.
CY_DSADC_VREF_POWER_LEVEL_HIGH	High power.
CY_DSADC_VREF_POWER_LEVEL_TURBO	Turbo power.

cy_en_dsadc_achan_trigger_synchronized_t

enum cy_en_dsadc_achan_trigger_synchronized_t

Configure the trigger synchronization.

Enumerator
CY_DSADC_ACHAN_TRIGGER_UNSYNCHRONIZED	Bypass clock domain synchronization of the trigger signal.
CY_DSADC_ACHAN_TRIGGER_SYNCHRONIZED	Synchronize the trigger signal to the Delta-Sigma Modulator (DSM) clock domain, if needed an edge detect is done in the peripheral clock domain.

cy_en_dsadc_dem_mode_t

enum cy_en_dsadc_dem_mode_t

The mode of dynamic element matching based dynamic element matching (DEM) scheme.

Enumerator
CY_DSADC_DEM_MODE_DWA	Data weighted averaging DWA mode.
CY_DSADC_DEM_MODE_ADWA	Alternate data weighted averaging DWA mode.
CY_DSADC_DEM_MODE_BIDWA	A bi-directional data weighted averaging Bi-DWA mode 78% power.

cy_en_dsadc_pga_power_level_t

enum cy_en_dsadc_pga_power_level_t

The power of the programmable gain amplifier (PGA).

Enumerator
CY_DSADC_PGA_POWER_LEVEL_39_PERCENT	Approximately 39% power.
CY_DSADC_PGA_POWER_LEVEL_58_PERCENT	Approximately 58% power.
CY_DSADC_PGA_POWER_LEVEL_78_PERCENT	Approximately 78% power.
CY_DSADC_PGA_POWER_LEVEL_100_PERCENT	Full Power.

cy_en_dsadc_achan_aaf_cutoff_freq_t

enum cy_en_dsadc_achan_aaf_cutoff_freq_t

Anti-Aliasing Filter (AAF) Cut-off Frequency.

Enumerator
CY_DSADC_ACHAN_AAF_CUTOFF_FREQ_30KHZ	30kHz
CY_DSADC_ACHAN_AAF_CUTOFF_FREQ_10KHZ	10kHz
CY_DSADC_ACHAN_AAF_CUTOFF_FREQ_20KHZ	20kHz

cy_en_dsadc_achan_chopping_type_t

enum cy_en_dsadc_achan_chopping_type_t

Configure the channel chopping type.

Enumerator
CY_DSADC_ACHAN_CHOPPING_OFF	Channel chopping disabled.
CY_DSADC_ACHAN_CHOPPING_CHANNEL	Channel chopping enabled. Chopping occurs between the inmux and modulator output using the modbit. The modbit toggles according to the modbit sample count.
CY_DSADC_ACHAN_CHOPPING_CROSS	Channel chopping enabled. Chopping occurs between the input and output of the buff using the modbit. The modbit toggles according to the modbit sample count.

cy_en_dsadc_achan0_2temp_trim_gain_type_t

enum cy_en_dsadc_achan0_2temp_trim_gain_type_t

The gain value to refer to the two temperature trim values for ACHAN0.

Enumerator
CY_DSADC_ACHAN0_2TEMP_GAIN_1X	The index for gain 1X.
CY_DSADC_ACHAN0_2TEMP_GAIN_2X	The index for gain 2X.
CY_DSADC_ACHAN0_2TEMP_GAIN_4X	The index for gain 4X.
CY_DSADC_ACHAN0_2TEMP_GAIN_8X	The index for gain 8X.
CY_DSADC_ACHAN0_2TEMP_GAIN_16X	The index for gain 16X.
CY_DSADC_ACHAN0_2TEMP_GAIN_32X	The index for gain 32X.
CY_DSADC_ACHAN0_2TEMP_GAIN_64X	The index for gain 64X.
CY_DSADC_ACHAN0_2TEMP_GAIN_128X	The index for gain 128X.
CY_DSADC_ACHAN0_2TEMP_GAIN_256X	The index for gain 256X.
CY_DSADC_ACHAN0_2TEMP_GAIN_512X	The index for gain 512X.

cy_en_dsadc_achan1_2temp_trim_gain_type_t

enum cy_en_dsadc_achan1_2temp_trim_gain_type_t

The gain value to refer to the two temperature trim values for ACHAN1.

Enumerator
CY_DSADC_ACHAN1_2TEMP_GAIN_0P5X	The index for gain 0.5X.
CY_DSADC_ACHAN1_2TEMP_GAIN_1X	The index for gain 1X.
CY_DSADC_ACHAN1_2TEMP_GAIN_2X	The index for gain 2X.
CY_DSADC_ACHAN1_2TEMP_GAIN_4X	The index for gain 4X.
CY_DSADC_ACHAN1_2TEMP_GAIN_8X	The index for gain 8X.
CY_DSADC_ACHAN1_2TEMP_GAIN_16X	The index for gain 16X.
CY_DSADC_ACHAN1_2TEMP_GAIN_32X	The index for gain 32X.
CY_DSADC_ACHAN1_2TEMP_GAIN_64X	The index for gain 64X.
CY_DSADC_ACHAN1_2TEMP_GAIN_128X	The index for gain 128X.
CY_DSADC_ACHAN1_2TEMP_GAIN_256X	The index for gain 256X.
CY_DSADC_ACHAN1_2TEMP_GAIN_512X	The index for gain 512X.

cy_en_dsadc_achan_3temp_trim_divider_type_t

enum cy_en_dsadc_achan_3temp_trim_divider_type_t

The divider output value to refer to the three temperature trim values for ACHAN.

Enumerator
CY_DSADC_ACHAN_3TEMP_VSENSE_16	The index for VSENSE/16.
CY_DSADC_ACHAN_3TEMP_VSENSE_24	The index for VSENSE/24.
CY_DSADC_ACHAN_3TEMP_VDIAG_16	The index for VDIAG/16.
CY_DSADC_ACHAN_3TEMP_VDIAG_24	The index for VDIAG/24.