COMMON Enumerated Types

Enumerations
enum	cy_en_dsadc_chopping_clock_divider_t {   CY_DSADC_CHOPPING_CLOCK_DIVIDER_2 = 0U,   CY_DSADC_CHOPPING_CLOCK_DIVIDER_4 = 1U,   CY_DSADC_CHOPPING_CLOCK_DIVIDER_8 = 2U,   CY_DSADC_CHOPPING_CLOCK_DIVIDER_16 = 3U,   CY_DSADC_CHOPPING_CLOCK_DIVIDER_32 = 4U,   CY_DSADC_CHOPPING_CLOCK_DIVIDER_64 = 5U,   CY_DSADC_CHOPPING_CLOCK_DIVIDER_128 = 6U,   CY_DSADC_CHOPPING_CLOCK_DIVIDER_256 = 7U }
	The divider for the chopping clock frequency. More...
enum	cy_en_dsadc_agc_aaf_blank_mode_t {   CY_DSADC_AGC_AAF_BLANK_MODE_SHORT = 0U,   CY_DSADC_AGC_AAF_BLANK_MODE_OPEN = 1U }
	Configure the behavior of the Anti-Aliasing Filter ( aaf) when the Automatic Gain Correction ( AGC) is updating the achan / dchan registers. More...
enum	cy_en_dsadc_ground_reference_t {   CY_DSADC_GROUND_REFERENCE_VSSA0 = 0U,   CY_DSADC_GROUND_REFERENCE_VSSA1 = 1U,   CY_DSADC_GROUND_REFERENCE_RSH = 2U,   CY_DSADC_GROUND_REFERENCE_RSL = 3U }
	Ground Reference options for Cy_DSADC_SetGroundReference. More...
enum	cy_en_dsadc_hpbgr_chopping_phase_t {   CY_DSADC_HPBGR_CHOPPING_PHASE_NORMAL = 0U,   CY_DSADC_HPBGR_CHOPPING_PHASE_REVERSE = 1U }
	Chopping Phase between the HPBGR "BGR Core" and the "output buffer". More...
enum	cy_en_dsadc_hpbgr_external_capacitor_t {   CY_DSADC_HPBGR_EXTERNAL_CAPACITOR_PRESENT = 0U,   CY_DSADC_HPBGR_EXTERNAL_CAPACITOR_ABSENT = 1U }
	Buffer phase compensation option for external capacitor. More...
enum	cy_en_dsadc_dchan_pga_gain_t {   CY_DSADC_DCHAN_PGA_GAIN_1X = 0U,   CY_DSADC_DCHAN_PGA_GAIN_2X = 1U,   CY_DSADC_DCHAN_PGA_GAIN_4X = 2U,   CY_DSADC_DCHAN_PGA_GAIN_8X = 3U,   CY_DSADC_DCHAN_PGA_GAIN_16X = 4U,   CY_DSADC_DCHAN_PGA_GAIN_32X = 5U }
	Configure the Digital Channel [DCHAN] PGA Gain. More...
enum	cy_en_dsadc_threshold_select_t {   CY_DSADC_HIGH_THRESHHOLD_CNTR = 0U,   CY_DSADC_LOW_THRESHHOLD_CNTR = 1U }
	Select high or low threshold counter. More...
enum	cy_en_dsadc_temperature_current_source_t {   CY_DSADC_TEMPERATURE_CURRENT_SOURCE_AREF = 0U,   CY_DSADC_TEMPERATURE_CURRENT_SOURCE_SRSS = 1U }
	Current source selection for the temperature sensor. More...
enum	cy_en_dsadc_temperature_load_mode_t {   CY_DSADC_TEMPERATURE_LOAD_MODE_PNP = 0U,   CY_DSADC_TEMPERATURE_LOAD_MODE_NPN = 1U,   CY_DSADC_TEMPERATURE_LOAD_MODE_RESISTOR = 2U }
	Load current configuration for the on-die temperature sensor. More...
enum	cy_en_dsadc_temperature_setup_t {   CY_DSADC_TEMPERATURE_CONFIG_PRIMARY = 0U,   CY_DSADC_TEMPERATURE_CONFIG_ALTERNATE = 1U }
	The temperature measurement parameters selection. More...
enum	cy_en_dsadc_temp_volt_meas_t {   CY_DSADC_TEMPERATURE_MEASUREMENT_RESISTOR = 0U,   CY_DSADC_TEMPERATURE_MEASUREMENT_TRANSISTOR = 1U }
	Target voltage measurement configuration selection. More...
enum	cy_en_dsadc_convert_source_t {   CY_DSADC_ACHAN0 = 0U,   CY_DSADC_ACHAN1 = 1U,   CY_DSADC_ALL_PRIMARY = 2U,   CY_DSADC_ALL_SECONDARY = 3U }
	Target to start convert selection. More...
enum	cy_en_dsadc_clock_edge_t {   CY_DSADC_CLOCK_EDGE_NEGATIVE = 0U,   CY_DSADC_CLOCK_EDGE_POSITIVE = 1U }
	Select clock edge: negative or positive. More...
enum	cy_en_dsadc_glitch_filter_mode_t {   CY_DSADC_GLITCH_FILTER_MODE_CONTINUOUS = 0U,   CY_DSADC_GLITCH_FILTER_MODE_UPDOWN = 1U }
	Select glitch filter mode: continuous or up/down. More...
enum	cy_en_dsadc_io_polarity_t {   CY_DSADC_IO_POLARITY_LOW = 0U,   CY_DSADC_IO_POLARITY_HIGH = 1U }
	Select IO polarity: low or high. More...
enum	cy_en_dsadc_ocd_threshold_t {   CY_DSADC_OCD_THRESH_37_5MV = 0U,   CY_DSADC_OCD_THRESH_40_0MV = 1U,   CY_DSADC_OCD_THRESH_42_5MV = 2U,   CY_DSADC_OCD_THRESH_45_0MV = 3U,   CY_DSADC_OCD_THRESH_47_5MV = 4U,   CY_DSADC_OCD_THRESH_50_0MV = 5U,   CY_DSADC_OCD_THRESH_50_0MV_A = 6U,   CY_DSADC_OCD_THRESH_50_0MV_B = 7U,   CY_DSADC_OCD_THRESH_75_0MV = 8U,   CY_DSADC_OCD_THRESH_80_0MV = 9U,   CY_DSADC_OCD_THRESH_85_0MV = 10U,   CY_DSADC_OCD_THRESH_90_0MV = 11U,   CY_DSADC_OCD_THRESH_95_0MV = 12U,   CY_DSADC_OCD_THRESH_100MV = 13U,   CY_DSADC_OCD_THRESH_100MV_A = 14U,   CY_DSADC_OCD_THRESH_100MV_B = 15U,   CY_DSADC_OCD_THRESH_150MV = 16U,   CY_DSADC_OCD_THRESH_160MV = 17U,   CY_DSADC_OCD_THRESH_170MV = 18U,   CY_DSADC_OCD_THRESH_180MV = 19U,   CY_DSADC_OCD_THRESH_190MV = 20U,   CY_DSADC_OCD_THRESH_200MV = 21U,   CY_DSADC_OCD_THRESH_200MV_A = 22U,   CY_DSADC_OCD_THRESH_200MV_B = 23U,   CY_DSADC_OCD_THRESH_200MV_C = 24U }
	The threshold for the overcurrent detection (OCD). More...
enum	cy_en_dsadc_ocd_clock_divider_t {   CY_DSADC_OCD_CLOCK_DIVIDER_2 = 0U,   CY_DSADC_OCD_CLOCK_DIVIDER_4 = 1U,   CY_DSADC_OCD_CLOCK_DIVIDER_6 = 2U,   CY_DSADC_OCD_CLOCK_DIVIDER_8 = 3U,   CY_DSADC_OCD_CLOCK_DIVIDER_10 = 4U,   CY_DSADC_OCD_CLOCK_DIVIDER_12 = 5U,   CY_DSADC_OCD_CLOCK_DIVIDER_14 = 6U,   CY_DSADC_OCD_CLOCK_DIVIDER_16 = 7U,   CY_DSADC_OCD_CLOCK_DIVIDER_18 = 8U,   CY_DSADC_OCD_CLOCK_DIVIDER_20 = 9U,   CY_DSADC_OCD_CLOCK_DIVIDER_22 = 10U,   CY_DSADC_OCD_CLOCK_DIVIDER_24 = 11U,   CY_DSADC_OCD_CLOCK_DIVIDER_26 = 12U,   CY_DSADC_OCD_CLOCK_DIVIDER_28 = 13U,   CY_DSADC_OCD_CLOCK_DIVIDER_30 = 14U,   CY_DSADC_OCD_CLOCK_DIVIDER_32 = 15U }
	The divider for OCD clock frequency. More...
enum	cy_en_dsadc_ocd_output_mode_t {   CY_DSADC_OCD_OUTPUT_MODE_DEFAULT = 0U,   CY_DSADC_OCD_OUTPUT_MODE_AND = 1U,   CY_DSADC_OCD_OUTPUT_MODE_OR = 2U }
	The OCD output mode. More...
enum	cy_en_dsadc_ocd_test_mode_t {   CY_DSADC_OCD_TST_DISABLED = 0U,   CY_DSADC_OCD_TST_PH_NH = 1U,   CY_DSADC_OCD_TST_PH_NL = 2U,   CY_DSADC_OCD_TST_PL_NH = 3U,   CY_DSADC_OCD_TST_PL_NL = 4U,   CY_DSADC_OCD_TST_PH_NH_NO_OUT = 5U,   CY_DSADC_OCD_TST_PH_NL_NO_OUT = 6U,   CY_DSADC_OCD_TST_PL_NH_NO_OUT = 7U,   CY_DSADC_OCD_TST_PL_NL_NO_OUT = 8U }
	Self Test mode. More...

Detailed Description

Enumeration Type Documentation

cy_en_dsadc_chopping_clock_divider_t

enum cy_en_dsadc_chopping_clock_divider_t

The divider for the chopping clock frequency.

Used for Modulator, programmable gain amplifier (PGA), and High-Precision BandGap Reference (HPBGR) chopping.

Enumerator
CY_DSADC_CHOPPING_CLOCK_DIVIDER_2	Chopping frequency is sampling frequency divided by 2.
CY_DSADC_CHOPPING_CLOCK_DIVIDER_4	Chopping frequency is sampling frequency divided by 4.
CY_DSADC_CHOPPING_CLOCK_DIVIDER_8	Chopping frequency is sampling frequency divided by 8.
CY_DSADC_CHOPPING_CLOCK_DIVIDER_16	Chopping frequency is sampling frequency divided by 16.
CY_DSADC_CHOPPING_CLOCK_DIVIDER_32	Chopping frequency is sampling frequency divided by 32.
CY_DSADC_CHOPPING_CLOCK_DIVIDER_64	Chopping frequency is sampling frequency divided by 64.
CY_DSADC_CHOPPING_CLOCK_DIVIDER_128	Chopping frequency is sampling frequency divided by 128.
CY_DSADC_CHOPPING_CLOCK_DIVIDER_256	Chopping frequency is sampling frequency divided by 256.

cy_en_dsadc_agc_aaf_blank_mode_t

enum cy_en_dsadc_agc_aaf_blank_mode_t

Configure the behavior of the Anti-Aliasing Filter ( aaf) when the Automatic Gain Correction ( AGC) is updating the achan / dchan registers.

Enumerator
CY_DSADC_AGC_AAF_BLANK_MODE_SHORT	Short the AAF resistor (close SW2 see aaf)
CY_DSADC_AGC_AAF_BLANK_MODE_OPEN	Disconnect AAF (open SW1 see aaf)

cy_en_dsadc_ground_reference_t

enum cy_en_dsadc_ground_reference_t

Ground Reference options for Cy_DSADC_SetGroundReference.

Note

Supported only on devices with a High Voltage Divider (see device datasheet).

Enumerator
CY_DSADC_GROUND_REFERENCE_VSSA0	Set the High Voltage Divider Ground Connection to VSSA. If VSSA is used, and VSSA is connected to the negative battery pole, then any voltage across the shunt resistor will appear as an offset voltage to chassis ground for the LIN pin. If VSSA is connected to chassis ground, then RSL / RSH should be used as the reference to avoid battery voltage measurement error.
CY_DSADC_GROUND_REFERENCE_VSSA1	Set the High Voltage Divider Ground Connection to VSSA. If VSSA is used, and VSSA is connected to the negative battery pole, then any voltage across the shunt resistor will appear as an offset voltage to chassis ground for the LIN pin. If VSSA is connected to chassis ground, then RSL / RSH should be used as the reference to avoid battery voltage measurement error.
CY_DSADC_GROUND_REFERENCE_RSH	Set the High Voltage Divider Ground Connection to RSH. The RSH Terminal is one of the terminals intended to be used with a shunt resistor to measure battery current. The orientation of RSH / RSL in hardware is dependent on the desired sign of the current charge / discharge. For charging current to be positive, RSH should be connected to ground.
CY_DSADC_GROUND_REFERENCE_RSL	Set the High Voltage Divider Ground Connection to RSL. Similar to RSH, this terminal is one of the terminals to use used with a shunt resistor to measure battery current. The orientation of RSH / RSL in hardware is dependent on the desired sign of the current charge / discharge. For discharging current to be positive, RSL should be connected to ground.

cy_en_dsadc_hpbgr_chopping_phase_t

enum cy_en_dsadc_hpbgr_chopping_phase_t

Chopping Phase between the HPBGR "BGR Core" and the "output buffer".

The HPBGR contains a "Band Gap Reference Core" (BGR Core) and an "output buffer", which are circuit chopped to reduce offset error.

The offset is reduced most when the BGR Core uses the opposite clock edge to chop when compared to the output buffer, which is referred to here as the 'reverse' chopping phase.

Optionally, the BGR Core and the output buffer can use the same clock edge for circuit chopping, referred to here as the 'normal' chopping phase.

Enumerator
CY_DSADC_HPBGR_CHOPPING_PHASE_NORMAL	The HPBGR 'Output Buffer' and the 'BGR Core' use the same chopping clock phase.
CY_DSADC_HPBGR_CHOPPING_PHASE_REVERSE	The HPBGR 'Output Buffer' and the 'BGR Core' use opposite chopping clock phase, reducing the offset between the two HPBGR internal components.

cy_en_dsadc_hpbgr_external_capacitor_t

enum cy_en_dsadc_hpbgr_external_capacitor_t

Buffer phase compensation option for external capacitor.

Buffer phase compensation option (external capacitor is present or absent).

Enumerator
CY_DSADC_HPBGR_EXTERNAL_CAPACITOR_PRESENT	External capacitor is present.
CY_DSADC_HPBGR_EXTERNAL_CAPACITOR_ABSENT	External capacitor is absent.

cy_en_dsadc_dchan_pga_gain_t

enum cy_en_dsadc_dchan_pga_gain_t

Configure the Digital Channel [DCHAN] PGA Gain.

Enumerator
CY_DSADC_DCHAN_PGA_GAIN_1X	Gain level 1X.
CY_DSADC_DCHAN_PGA_GAIN_2X	Gain level 2X.
CY_DSADC_DCHAN_PGA_GAIN_4X	Gain level 4X.
CY_DSADC_DCHAN_PGA_GAIN_8X	Gain level 8X.
CY_DSADC_DCHAN_PGA_GAIN_16X	Gain level 16X.
CY_DSADC_DCHAN_PGA_GAIN_32X	Gain level 32X.

cy_en_dsadc_threshold_select_t

enum cy_en_dsadc_threshold_select_t

Select high or low threshold counter.

Enumerator
CY_DSADC_HIGH_THRESHHOLD_CNTR	Used to get status of High threshold counter.
CY_DSADC_LOW_THRESHHOLD_CNTR	Used to get status of Low threshold counter.

cy_en_dsadc_temperature_current_source_t

enum cy_en_dsadc_temperature_current_source_t

Current source selection for the temperature sensor.

Enumerator
CY_DSADC_TEMPERATURE_CURRENT_SOURCE_AREF	Use the AREF as the current source.
CY_DSADC_TEMPERATURE_CURRENT_SOURCE_SRSS	Use the SRSS as the current source.

cy_en_dsadc_temperature_load_mode_t

enum cy_en_dsadc_temperature_load_mode_t

Load current configuration for the on-die temperature sensor.

Enumerator
CY_DSADC_TEMPERATURE_LOAD_MODE_PNP	Configure for PNP, for user temperature measurements.
CY_DSADC_TEMPERATURE_LOAD_MODE_NPN	Configure for NPN, for factory calibration.
CY_DSADC_TEMPERATURE_LOAD_MODE_RESISTOR	Configure for the internal resistor (5k Ohms).

cy_en_dsadc_temperature_setup_t

enum cy_en_dsadc_temperature_setup_t

The temperature measurement parameters selection.

Enumerator
CY_DSADC_TEMPERATURE_CONFIG_PRIMARY	Select primary temperature measurement parameters.
CY_DSADC_TEMPERATURE_CONFIG_ALTERNATE	Select alternate temperature measurement parameters.

cy_en_dsadc_temp_volt_meas_t

enum cy_en_dsadc_temp_volt_meas_t

Target voltage measurement configuration selection.

Enumerator
CY_DSADC_TEMPERATURE_MEASUREMENT_RESISTOR	Configure target voltage measurement across resistor (5k Ohms).
CY_DSADC_TEMPERATURE_MEASUREMENT_TRANSISTOR	Configure target voltage measurement across bipolar transistor (PNP/NPN).

cy_en_dsadc_convert_source_t

enum cy_en_dsadc_convert_source_t

Target to start convert selection.

Enumerator
CY_DSADC_ACHAN0	Start convert ACHAN0.
CY_DSADC_ACHAN1	Start convert ACHAN1.
CY_DSADC_ALL_PRIMARY	Start convert all Primary channels.
CY_DSADC_ALL_SECONDARY	Start convert all Secondary channels.

cy_en_dsadc_clock_edge_t

enum cy_en_dsadc_clock_edge_t

Select clock edge: negative or positive.

Enumerator
CY_DSADC_CLOCK_EDGE_NEGATIVE	Negative clock edge.
CY_DSADC_CLOCK_EDGE_POSITIVE	Positive clock edge.

cy_en_dsadc_glitch_filter_mode_t

enum cy_en_dsadc_glitch_filter_mode_t

Select glitch filter mode: continuous or up/down.

Enumerator
CY_DSADC_GLITCH_FILTER_MODE_CONTINUOUS	Continuous glitch filter mode.
CY_DSADC_GLITCH_FILTER_MODE_UPDOWN	Up/down glitch filter mode.

cy_en_dsadc_io_polarity_t

enum cy_en_dsadc_io_polarity_t

Select IO polarity: low or high.

Enumerator
CY_DSADC_IO_POLARITY_LOW	IO polarity low.
CY_DSADC_IO_POLARITY_HIGH	IO polarity high.

cy_en_dsadc_ocd_threshold_t

enum cy_en_dsadc_ocd_threshold_t

The threshold for the overcurrent detection (OCD).

Each value corresponds to a specific voltage threshold in millivolts.

Note

Some threshold values have multiple variants (A, B, C) that map to the same voltage level to handle reserved hardware bit combinations safely.

Enumerator
CY_DSADC_OCD_THRESH_37_5MV	Overcurrent threshold: 37.5 mV.
CY_DSADC_OCD_THRESH_40_0MV	Overcurrent threshold: 40.0 mV.
CY_DSADC_OCD_THRESH_42_5MV	Overcurrent threshold: 42.5 mV.
CY_DSADC_OCD_THRESH_45_0MV	Overcurrent threshold: 45.0 mV.
CY_DSADC_OCD_THRESH_47_5MV	Overcurrent threshold: 47.5 mV.
CY_DSADC_OCD_THRESH_50_0MV	Overcurrent threshold: 50.0 mV.
CY_DSADC_OCD_THRESH_50_0MV_A	Overcurrent threshold: 50.0 mV (variant A).
CY_DSADC_OCD_THRESH_50_0MV_B	Overcurrent threshold: 50.0 mV (variant B).
CY_DSADC_OCD_THRESH_75_0MV	Overcurrent threshold: 75.0 mV.
CY_DSADC_OCD_THRESH_80_0MV	Overcurrent threshold: 80.0 mV.
CY_DSADC_OCD_THRESH_85_0MV	Overcurrent threshold: 85.0 mV.
CY_DSADC_OCD_THRESH_90_0MV	Overcurrent threshold: 90.0 mV.
CY_DSADC_OCD_THRESH_95_0MV	Overcurrent threshold: 95.0 mV.
CY_DSADC_OCD_THRESH_100MV	Overcurrent threshold: 100.0 mV.
CY_DSADC_OCD_THRESH_100MV_A	Overcurrent threshold: 100.0 mV (variant A).
CY_DSADC_OCD_THRESH_100MV_B	Overcurrent threshold: 100.0 mV (variant B).
CY_DSADC_OCD_THRESH_150MV	Overcurrent threshold: 150.0 mV.
CY_DSADC_OCD_THRESH_160MV	Overcurrent threshold: 160.0 mV.
CY_DSADC_OCD_THRESH_170MV	Overcurrent threshold: 170.0 mV.
CY_DSADC_OCD_THRESH_180MV	Overcurrent threshold: 180.0 mV.
CY_DSADC_OCD_THRESH_190MV	Overcurrent threshold: 190.0 mV.
CY_DSADC_OCD_THRESH_200MV	Overcurrent threshold: 200.0 mV.
CY_DSADC_OCD_THRESH_200MV_A	Overcurrent threshold: 200.0 mV (variant A).
CY_DSADC_OCD_THRESH_200MV_B	Overcurrent threshold: 200.0 mV (variant B).
CY_DSADC_OCD_THRESH_200MV_C	Overcurrent threshold: 200.0 mV (variant C).

cy_en_dsadc_ocd_clock_divider_t

enum cy_en_dsadc_ocd_clock_divider_t

The divider for OCD clock frequency.

Uses the DSM clock (clk_dsm) to create OCD clock using the following formula: Focd = Fclk_dsm / (2*(CLOCK_DIV+1))

Enumerator
CY_DSADC_OCD_CLOCK_DIVIDER_2	OCD frequency is DSM frequency divided by 2.
CY_DSADC_OCD_CLOCK_DIVIDER_4	OCD frequency is DSM frequency divided by 4.
CY_DSADC_OCD_CLOCK_DIVIDER_6	OCD frequency is DSM frequency divided by 6.
CY_DSADC_OCD_CLOCK_DIVIDER_8	OCD frequency is DSM frequency divided by 8.
CY_DSADC_OCD_CLOCK_DIVIDER_10	OCD frequency is DSM frequency divided by 10.
CY_DSADC_OCD_CLOCK_DIVIDER_12	OCD frequency is DSM frequency divided by 12.
CY_DSADC_OCD_CLOCK_DIVIDER_14	OCD frequency is DSM frequency divided by 14.
CY_DSADC_OCD_CLOCK_DIVIDER_16	OCD frequency is DSM frequency divided by 16.
CY_DSADC_OCD_CLOCK_DIVIDER_18	OCD frequency is DSM frequency divided by 18.
CY_DSADC_OCD_CLOCK_DIVIDER_20	OCD frequency is DSM frequency divided by 20.
CY_DSADC_OCD_CLOCK_DIVIDER_22	OCD frequency is DSM frequency divided by 22.
CY_DSADC_OCD_CLOCK_DIVIDER_24	OCD frequency is DSM frequency divided by 24.
CY_DSADC_OCD_CLOCK_DIVIDER_26	OCD frequency is DSM frequency divided by 26.
CY_DSADC_OCD_CLOCK_DIVIDER_28	OCD frequency is DSM frequency divided by 28.
CY_DSADC_OCD_CLOCK_DIVIDER_30	OCD frequency is DSM frequency divided by 30.
CY_DSADC_OCD_CLOCK_DIVIDER_32	OCD frequency is DSM frequency divided by 32.

cy_en_dsadc_ocd_output_mode_t

enum cy_en_dsadc_ocd_output_mode_t

The OCD output mode.

Only applicable for OCD0. In any mode other than the default it is used to condense both the OCD0 output and the OCD1 output onto OCD0 pin.

Enumerator
CY_DSADC_OCD_OUTPUT_MODE_DEFAULT	OCD0 output pin = OCD0.
CY_DSADC_OCD_OUTPUT_MODE_AND	OCD0 output pin = OCD0 && OCD1.
CY_DSADC_OCD_OUTPUT_MODE_OR	OCD0 output pin = OCD0 || OCD1.

cy_en_dsadc_ocd_test_mode_t

enum cy_en_dsadc_ocd_test_mode_t

Self Test mode.

Controls bypassing the input to the detector from the comparator per pos/neg. Also, enables/disables output to GPIO, interrupt and trigger infra depending on selected mode.

Enumerator
CY_DSADC_OCD_TST_DISABLED	Self Test is disabled.
CY_DSADC_OCD_TST_PH_NH	Self Test enabled by bypass positive with High level negative with High level and out enabled.
CY_DSADC_OCD_TST_PH_NL	Self Test enabled by bypass positive with High level negative with Low level and out enabled.
CY_DSADC_OCD_TST_PL_NH	Self Test enabled by bypass positive with Low level negative with High level and out enabled.
CY_DSADC_OCD_TST_PL_NL	Self Test enabled by bypass positive with Low level negative with Low level and out enabled.
CY_DSADC_OCD_TST_PH_NH_NO_OUT	Self Test enabled by bypass positive with High level negative with High level and out disabled.
CY_DSADC_OCD_TST_PH_NL_NO_OUT	Self Test enabled by bypass positive with High level negative with Low level and out disabled.
CY_DSADC_OCD_TST_PL_NH_NO_OUT	Self Test enabled by bypass positive with Low level negative with High level and out disabled.
CY_DSADC_OCD_TST_PL_NL_NO_OUT	Self Test enabled by bypass positive with Low level negative with Low level and out disabled.