WDC (Watchdog Counters)

Watchdog Counters (WDC) are general-purpose timers clocked from a low- frequency clock source and capable of generating interrupts. More...

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Detailed Description

Watchdog Counters (WDC) are general-purpose timers clocked from a low- frequency clock source and capable of generating interrupts.

Features:

• Two 16-bit and one 32-bit counters
• Can be configured to generate periodic interrupts
• Can be clocked from ILO or WCO
• Counters can be cascaded to achieve a bigger period
• Can work in Sleep and Deep Sleep power modes

The functions and other declarations used in this driver are in cy_wdc.h. You can include cy_pdl.h to get access to all functions and declarations in the PDL.

There are two primary use cases for WDC: generating periodic CPU interrupts; and implementing a free-running timer. Both have many applications in embedded systems:

• Measuring time between events
• Generating periodic events
• Synchronizing actions
• Real-time clocking
• Polling.

Configuration Considerations

The WDC block contains three sub-counters, each of which can be configured for one of the system utility functions - free running counter or periodic interrupts.

A simplified diagram of the WDC hardware is shown below:

The frequency of the periodic interrupts for C0 and C1 counters can be configured using the Match value using Cy_WDC_SetMatch() together with Clear on match option, which can be set using Cy_WDC_SetClearOnMatch() function. When Clear on match option is not set, the periodic interrupts of the C0 and C1 16-bit sub-counters occur after 65535 counts and the match value defines the shift between interrupts (see the figure below). The enabled Clear on match option resets the counter when the interrupt occurs.

Clear on match is disabled:

Clear on match is enabled:

32-bit sub-counter C2 does not have the Clear on match option. The interrupt of counter C2 occurs when the counts equal 2^{Toggle bit} value. For example: when toggle bit = 0, C2 will generate interrupt every WDC clock source rising edge; when toggle bit = 31, C2 will generate interrupt every 2³¹ WDC clock source rising edge.

WDC initialization can be divided into a number of sequential steps listed below:

• Configure WDC
• Counters Cascading
• Configure Interrupt
• Enable Counters

Configure WDC

To set up a WDC, provide the configuration parameters in the cy_stc_wdc_config_t structure. Then call Cy_WDC_Init() to initialize the driver.

    cy_stc_wdc_config_t wdcConfig =
    {
        /* counter0Match        */ 39999U,              /* Divide ILO to 1 sec period (40KHz ILO) */
        /* counter1Match        */ 0U,                  /* Not used */
        /* counter2ToggleBit    */ 0U,                  /* Not used */
        /* counter0Interrupt    */ true,                /* Enable counter 1 interrupt */
        /* counter1Interrupt    */ false,               /* Not used */
        /* counter2Interrupt    */ false,               /* Not used */
        /* counter0ClearOnMatch */ true,                /* Clean on match for counter 0 to use as configurable divider */
        /* counter1ClearOnMatch */ false,               /* Not used */
        /* countersCascade      */ CY_WDC_CASCADE_NONE, /* No cascading */
        /* clockSource          */ CY_WDC_CLOCK_ILO,    /* Use ILO as clock source */
    };
    
    Cy_WDC_Init(WCO, &wdcConfig);

Note

Before initialization of WDC, ensure that the selected WDC clock source is enabled. Refer to Internal Low-Speed Oscillator (ILO) and Watch Crystal Oscillator (WCO) sections of SysClk driver documentation.

Counters Cascading

The WDC counter can be cascaded in order to achieve longer wait periods. When a counter is cascaded, it uses the previous counter event signal in order to perform the increment operation instead of the WDC clock source. For example, to configure a WDC to generate interrupts approx. every 20 seconds using ILO clock source (40KHz), the total timer period should be set to 40000 * 20 = 800000 counts, which is above the 16-bit single timer resolution. For a long period delays, 32-bit counter 2 can be used, but it only allows fixed period values. In our case, it will generate interrupts with 13.1 seconds (2^19 = 524288) or 26.2 seconds (2^20 = 1048576) periods. To achieve higher timing precision, counters 0 and 1 can be cascaded. In this case, the following configuration structure can be used:

cy_stc_wdc_config_t wdcConfigCascade =
{
    /* counter0Match        */ 39999U,                      /* Divide ILO to 1 sec period (40KHz ILO) */
    /* counter1Match        */ 20U,                         /* Divide 1 sec period form counter 0 to form 20 sec period*/
    /* counter2ToggleBit    */ 0U,                          /* Not used */
    /* counter0Interrupt    */ false,                       /* Disable counter 0 interrupt */
    /* counter1Interrupt    */ true,                        /* Enable counter 1 interrupt */
    /* counter2Interrupt    */ false,                       /* Not used */
    /* counter0ClearOnMatch */ true,                        /* Clean on match for counter 0 to use as configurable divider */
    /* counter1ClearOnMatch */ true,                        /* Clean on match for counter 0 to use as configurable divider */
    /* countersCascade      */ CY_WDC_CASCADE_COUNTERS01,   /* Cascade 0 and 1 counters */
    /* clockSource          */ CY_WDC_CLOCK_ILO,            /* Use ILO as clock source */
};

Alternatively, the same settings can be applied using the corresponding WDC functions after calling the Cy_WDC_Init function. Refer to Functions for details.

There are four possible cascading options:

• CY_WDC_CASCADE_NONE - all counters work independently
• CY_WDC_CASCADE_COUNTERS01 - counters 0 and 1 are cascaded. If Clean on match is set for both counters total cascaded period will be equal to (C0_Match + 1) * C1_Match
• CY_WDC_CASCADE_COUNTERS12 - counters 1 and 2 are cascaded. If Clean on match is set for counter 1 total cascaded period will be equal to (C1_Match + 1) * 2^{C2_Toggle_bit}
• CY_WDC_CASCADE_ALL - counters 0, 1 and 2 are cascaded. If Clean on match is set for counters 0 and 1 counters total cascaded period will be equal to (C0_Match + 1) * C1_Match * 2^{C2_Toggle_bit}.

Configure Interrupt

All counter interrupts are OR'd together to form a single combined WDC interrupt. To configure a WDC interrupt, initialize the referenced interrupt by setting the priority and the interrupt vector using Cy_SysInt_Init() of the SysInt driver and provide interrupt handler:

void WDC_Isr(void)
{
    uint32_t intStatus = Cy_WDC_GetInterruptStatus(WCO);
    Cy_WDC_ClearInterrupt(WCO, intStatus);
    
    if(0U != (intStatus & CY_WDC_COUNTER0_Msk))
    {
        /* Process counter 0 interrupt */
    }
    
    if(0U != (intStatus & CY_WDC_COUNTER1_Msk))
    {
        /* Process counter 1 interrupt */
    }
    
    if(0U != (intStatus & CY_WDC_COUNTER2_Msk))
    {
        /* Process counter 2 interrupt */
    }
}

    /* Configuration structure for WDC interrupt */
    cy_stc_sysint_t wdcIrqCfg =
    {
        .intrSrc = wco_interrupt_IRQn,
        .intrPriority = 3U,
    };
    
    /* Assign interrupt handler function and set interrupt priority */
    if (CY_SYSINT_SUCCESS != Cy_SysInt_Init(&wdcIrqCfg, WDC_Isr))
    {
        /* Insert the error handling here */
    }
    
    /* Enable the WDC interrupt */
    NVIC_EnableIRQ(wdcIrqCfg.intrSrc);

Additionally, global interrupts should be enabled.

Enable Counters

The last configuration step enables the configured counters using Cy_WDC_Enable function.

    /* Enable counter 0 */
    Cy_WDC_Enable(WCO, CY_WDC_COUNTER0_Msk, CY_WDC_CLK_ILO_3CYCLES_US);

Note

In addition to WDCs, each device has a separate watchdog timer (WDT) to generate a watchdog reset or periodic interrupts. For detail on the WDT, see WDT (Watchdog Timer) section.

More Information

For detail on the WDC peripheral, refer to the technical reference manual (TRM).

Changelog

Version	Changes	Reason for Change
1.0.2	Update the paths to the code snippets.	PDL structure update.
1.0.1	Corrected source code comments text.
1.0	Initial version