Shift Register Disabled Output

General Description

Specifies the behavior of the Shift Register outputs while Shift Register is disabled.

Macros
#define	CY_TCPWM_SHIFTREG_OUTPUT_HIGHZ   (0U)
	Shift Register output (default) high impedance.
#define	CY_TCPWM_SHIFTREG_OUTPUT_RETAIN   (1U)
	Shift Register outputs are retained.
#define	CY_TCPWM_SHIFTREG_OUTPUT_LOW   (2U)
	Shift Register output LOW.
#define	CY_TCPWM_SHIFTREG_OUTPUT_HIGH   (3U)
	Shift Register output HIGH.