Provides device startup, system configuration, and linker script files.
The system startup provides the followings features:
The flash and RAM allocation for each CPU is defined by the linker scripts. For dual-core devices, the physical flash and RAM memory is shared between the CPU cores. 2 KB of RAM (allocated at the end of RAM) are reserved for system use. For Single-Core devices the system reserves additional 80 bytes of RAM. Using the reserved memory area for other purposes will lead to unexpected behavior.
ARM GCC
The flash and RAM sections for the CPU are defined in the linker files: 'xx_yy.ld', where 'xx' is the device group, and 'yy' is the target CPU; for example, 'cy8c6xx7_cm0plus.ld' and 'cy8c6xx7_cm4_dual.ld'.
Change the flash and RAM sizes by editing the macros value in the linker files for both CPUs:
Change the value of the CY_CORTEX_M4_APPL_ADDR macro to the ROM ORIGIN's value (0x10000000) + FLASH_CM0P_SIZE value (0x2000, the size of a flash image of the Cortex-M0+ application should be the same value as the flash LENGTH in 'xx_cm0plus.ld') in the 'xx_cm4_dual.ld' file, where 'xx' is the device group. Do this by either:
ARM Compiler
The flash and RAM sections for the CPU are defined in the linker files: 'xx_yy.sct', where 'xx' is the device group, and 'yy' is the target CPU; for example 'cy8c6xx7_cm0plus.sct' and 'cy8c6xx7_cm4_dual.sct'.
Change the flash and RAM sizes by editing the macros value in the linker files for both CPUs:
Change the value of the CY_CORTEX_M4_APPL_ADDR macro to the FLASH_START value (0x10000000) + FLASH_CM0P_SIZE value (0x2000, the size of a flash image of the Cortex-M0+ application should be the same value as the FLASH_SIZE in the 'xx_cm0plus.sct') in the 'xx_cm4_dual.sct' file, where 'xx' is the device group. Do this by either:
IAR
The flash and RAM sections for the CPU are defined in the linker files: 'xx_yy.icf', where 'xx' is the device group, and 'yy' is the target CPU; for example, 'cy8c6xx7_cm0plus.icf' and 'cy8c6xx7_cm4_dual.icf'.
Change the flash and RAM sizes by editing the macros value in the linker files for both CPUs:
Change the value of the CY_CORTEX_M4_APPL_ADDR macro to the ICFEDIT_region_IROM1_start value (0x10000000) + FLASH_CM0P_SIZE value (0x2000, the size of a flash image of the Cortex-M0+ application) in the 'xx_cm4_dual.icf' file, where 'xx' is the device group. The sum result should be the same as (ICFEDIT_region_IROM1_end + 1) value in the 'xx_cm0plus.icf'. Do this by either:
After a power-on-reset (POR), the boot process is handled by the boot code from the on-chip ROM that is always executed by the Cortex-M0+ core. The boot code passes the control to the Cortex-M0+ startup code located in flash.
The Cortex-M0+ startup code performs the device initialization by a call to SystemInit() and then calls the main() function. The Cortex-M4 core is disabled by default. Enable the core using the Cy_SysEnableCM4() function. See Cortex-M4 Control Functions for more details.
The Cortex-M0+ core is not user-accessible on these devices. In this case the Flash Boot handles setup of the CM0+ core and starts the Cortex-M4 core.
There are two ways to adjust heap and stack configurations:
By default, the stack size is set to 0x00001000 and the heap size is allocated dynamically to the whole available free memory up to stack memory and it is set to the 0x00000400 (for ARM GCC and IAR compilers) as minimal value.
The default interrupt handler functions are defined as weak functions to a dummy handler in the startup file. The naming convention for the interrupt handler names is <interrupt_name>_IRQHandler. A default interrupt handler can be overwritten in user code by defining the handler function using the same name. For example:
This process uses memory sections defined in the linker script. The startup code actually defines the contents of the vector table and performs the copy.
The linker script file is 'xx_yy.ld', where 'xx' is the device family, and 'yy' is the target CPU; for example, cy8c6xx7_cm0plus.ld and cy8c6xx7_cm4_dual.ld. It defines sections and locations in memory.
Copy interrupt vectors from flash to RAM:
From:
To:
Size:
The vector table address (and the vector table itself) are defined in the assembler startup files (e.g. startup_psoc6_01_cm0plus.S and startup_psoc6_01_cm4.S). The code in these files copies the vector table from Flash to RAM.
The linker script file is 'xx_yy.sct', where 'xx' is the device family, and 'yy' is the target CPU; for example, cy8c6xx7_cm0plus.sct and cy8c6xx7_cm4_dual.sct. The linker script specifies that the vector table (RESET_RAM) shall be first in the RAM section.
RESET_RAM represents the vector table. It is defined in the assembler startup files (e.g. startup_psoc6_01_cm0plus.s and startup_psoc6_01_cm4.s). The code in these files copies the vector table from Flash to RAM.
The linker script file is 'xx_yy.icf', where 'xx' is the device family, and 'yy' is the target CPU; for example, cy8c6xx7_cm0plus.icf and cy8c6xx7_cm4_dual.icf. This file defines the .intvec_ram section and its location.
The vector table address (and the vector table itself) are defined in the assembler startup files (e.g. startup_psoc6_01_cm0plus.s and startup_psoc6_01_cm4.s). The code in these files copies the vector table from Flash to RAM.
MISRA Rule | Rule Class (Required/Advisory) | Rule Description | Description of Deviation(s) |
---|---|---|---|
2.3 | R | The character sequence // shall not be used within a comment. | The comments provide a useful WEB link to the documentation. |
Version | Changes | Reason for Change |
---|---|---|
2.100 | Added support for TRAVEO™ II Body Entry devices. | Code enhancement and support for new devices. |
2.95.1 | Restructured documentation. | Documentation update. |
2.95 | Update FPU enable function with CMSIS macros to disable/enable interrupts | Move to stadnard inline CMSIS ARM macros |
2.91 | Updated memory configuration for PSoC 64 devices. | Flash and RAM memory allocation updated. |
Added cys06xxa_cm4 linker scripts. | New device support. | |
2.90.1 | Updated ARM GCC section with the note on the dynamic memory allocation for ARM GCC. | Documentation update. |
Updated system_psoc6.h to include custom CY_SYSTEM_PSOC6_CONFIG passed as compiler macro. | Improve configuration flexibility. | |
Updated attribute usage for the linker section placement in CM0+ startup code | Enhancement based on usability feedback. | |
Renamed the '.cy_xip' linker script region as 'cy_xip' | Enable access to the XIP region start/end addresses from the C code. | |
2.90 | Updated linker scripts for PSoC 64 Secure MCU cyb06xx7 devices. | Flash allocation adjustment. |
2.80 | Updated linker scripts for PSoC 64 Secure MCU devices. | Updated FLASH and SRAM memory area definitions in cyb0xxx linker script templates in accordance with the PSoC 64 Secure Boot SDK policies. |
Added Cy_PRA_Init() call to SystemInit() Cortex-M0+ and Cortex-M4 functions for PSoC 64 Secure MCU. | Updated PSoC 64 Secure MCU startup sequence to initialize the Protected Register Access driver. | |
2.70.1 | Updated documentation for the better description of the existing startup implementation. | User experience enhancement. |
2.70 | Updated SystemCoreClockUpdate() implementation - The SysClk API is reused. | Code optimization. |
Updated SystemInit() implementation - The IPC7 structure is initialized for both cores. | Provided support for SysPM driver updates. | |
Updated the linker scripts. | Reserved FLASH area for the MCU boot headers. | |
Added System Pipe initialization for all devices. | Improved PDL usability according to user experience. | |
Removed redundant legacy macros: CY_CLK_EXT_FREQ_HZ, CY_CLK_ECO_FREQ_HZ and CY_CLK_ALTHF_FREQ_HZ. Use Cy_SysClk_ExtClkSetFrequency, Cy_SysClk_EcoConfigure and Cy_BLE_EcoConfigure functions instead them. | Defect fixing. | |
2.60 | Updated linker scripts. | Provided support for new devices, updated usage of CM0p prebuilt image. |
2.50 | Updated assembler files, C files, linker scripts. | Dynamic allocated HEAP size for Arm Compiler 6, IAR 8. |
2.40 | Updated assembler files, C files, linker scripts. | Added Arm Compiler 6 support. |
2.30 | Added assembler files, linker scripts for Mbed OS. | Added Arm Mbed OS embedded operating system support. |
Updated linker scripts to extend the Flash and Ram memories size available for the CM4 core. | Enhanced PDL usability. | |
2.20 | Moved the Cy_IPC_SystemSemaInit(), Cy_IPC_SystemPipeInit() functions implementation from IPC to Startup. | Changed the IPC driver configuration method from compile time to run time. |
2.10 | Added constructor attribute to SystemInit() function declaration for ARM MDK compiler. Removed $Sub$$main symbol for ARM MDK compiler. | uVision Debugger support. |
Updated description of the Startup behavior for Single-Core Devices. Added note about WDT disabling by SystemInit() function. | Documentation improvement. | |
2.0 | Added restoring of FLL registers to the default state in SystemInit() API for single core devices. Single core device support. | |
Added Normal Access Restrictions, Public Key, TOC part2 and TOC part2 copy to Supervisory flash linker memory regions. Renamed 'wflash' memory region to 'em_eeprom'. | Linker scripts usability improvement. | |
Added Cy_IPC_SystemSemaInit(), Cy_IPC_SystemPipeInit(), Cy_Flash_Init() functions call to SystemInit() API. | Reserved system resources for internal operations. | |
Added clearing and releasing of IPC structure #7 (reserved for the Deep-Sleep operations) to SystemInit() API. | To avoid deadlocks in case of SW or WDT reset during Deep-Sleep entering. | |
1.0 | Initial version |
API Reference | |
Macros | |
Functions | |
Global Variables | |