SysInt (System Interrupt)

General Description

The SysInt driver provides an API to configure the device peripheral interrupts.

It provides a lightweight interface to complement the CMSIS core NVIC API. The provided functions are applicable for all cores in a device and they can be used to configure and connect device peripheral interrupts to one or more cores.

The functions and other declarations used in this driver are in cy_sysint.h. You can include cy_pdl.h to get access to all functions and declarations in the PDL.

Vector Table

CM0+/CM4

The vector table defines the entry addresses of the processor exceptions and the device specific interrupts. It is located at the start address of the flash and is copied by the startup code to RAM. The symbol code __Vectors is the address of the vector table in the startup code and the register SCB->VTOR holds the start address of the vector table. See Vectors Table Copy from Flash to RAM section for the implementation details. The default interrupt handler functions are defined as weak functions to a dummy handler in the startup file. The naming convention is <interrupt_name>_IRQHandler.

Defining these in the user application allows the linker to place them in the vector table in flash/ROM. For example:

void ioss_interrupts_gpio_0_IRQHandler(void)
{
    ...
}

And can be used like this:

    /* Scenario: Vector table is not relocated anywhere from _Vectors[] in flash */

#if (CY_CPU_CORTEX_M0P)
    /* Prototype of ISR function for NvicMux7, defined as a weak function in startup_psoc0x_cm0plus.s */
    void NvicMux7_IRQHandler(void);

#else
    /* Prototype of ISR function for gpio interrupt 0, defined as a weak function in startup_psoc0x_cm4.s */
    void ioss_interrupts_gpio_0_IRQHandler(void);

#endif

    /* Initialize the interrupt with vector at Interrupt_Handler_Port0() */
    Cy_SysInt_Init(&intrCfg, (cy_israddress)NULL);

    /* Enable the interrupt */
    NVIC_EnableIRQ(intrCfg.intrSrc);

Using this method avoids the need for a RAM vector table. However in this scenario, interrupt handler re-location at run-time is not possible, unless the vector table is relocated to RAM.

CM33

CM33 with Security extension supports two vector tables, one for secure world and another for non-secure world. Secure interrupt vector table is placed in the secure ROM/FLASH, where as non-secure interrupt vector table is placed in the non-secure ROM/FLASH. In both scenarios, vector tables are copied by the startup code to secure and non-secure RAM respectively. The symbol code __s_vector_table is the address of the secure vector table and __ns_vector_table is for the non-secure world in the startup code. The register SCB->VTOR holds the start address of the vector table. See Vectors Table Copy from Flash to RAM section for the implementation details.

CM33 without Security extension will support only non-secure interrupts.

The default interrupt handler functions are defined to a dummy handler in the startup file. The naming convention is <interrupt_name>_IRQHandler.

CM55

CM55 is without Security extension and will support only non-secure interrupts. It is similar to CM33 non-secure part. Additionally CM55 core has support to block EWIC (External Wakeup Interrupt Controller). EWIC is a peripheral to the processor and it can be a source of wakeup in the system. EWIC block is disabled by default and needs to be enabled in order for the DS wakeup source to work.

CAT1C CM0+/CM7

The vector table defines the entry addresses of the processor exceptions and the device specific interrupts. Interrupt vector table is placed in the ROM/FLASH. The vector table is copied by the startup code to RAM. The symbol code __ramVectors is the address of the vector table. The register SCB->VTOR holds the start address of the vector table. See Vectors Table Copy from Flash to RAM section for the implementation details. Each system interrupt has to be mapped onto one out of eight external CPU interrupts. When a system interrupt is triggered, corresponding mapped CPU IRQ gets triggered which results in the execution of the default CPU IRQ handler. In this handler the system interrupt mapped to this CPU interrupt will be fetched and executed.

The default CPU IRQ handler functions are defined as weak functions in the startup file. The naming convention followed is <core>_CpuIntr<interrupt_number>_Handler. Below is the code snippet.

void Interrupt_Handler_Port0(void)
{
    ... //User interrupt handler
}

    /* Scenario: Vector table is relocated to RAM in __ramVectors[] */

    /* Prototype of ISR function for port interrupt 0. For CY_IP_M7CPUSS port 21 is configured */
    void Interrupt_Handler_Port0 (void);

    /* Initialize the interrupt with vector at Interrupt_Handler_Port0() */
    Cy_SysInt_Init(&intrCfg, &Interrupt_Handler_Port0);

    /* Enable the interrupt */
#if (CY_IP_M7CPUSS)
    NVIC_EnableIRQ((IRQn_Type) NvicMux3_IRQn);
#else
    NVIC_EnableIRQ(intrCfg.intrSrc);
#endif

Driver Usage

Initialization

Interrupt numbers are defined in a device-specific header file, such as cy8c68237bz_ble.h, and are consistent with interrupt handlers defined in the vector table.

To configure an interrupt, call Cy_SysInt_Init(). Populate the configuration structure (cy_stc_sysint_t) and pass it as a parameter along with the ISR address. This initializes the interrupt and instructs the CPU to jump to the specified ISR vector upon a valid trigger. For CM0+ core, the configuration structure (cy_stc_sysint_t) must specify the device interrupt source (cm0pSrc) that feeds into the CM0+ NVIC mux (intrSrc).

For CM4/CM33/CM55 core, system interrupt source 'n' is connected to the corresponding IRQn. Deep-sleep capable interrupts are allocated to Deep Sleep capable IRQn channels.

For CAT1C CM7/CM0+ core, the configuration structure (cy_stc_sysint_t) must specify system interrupt source, CPU IRQ and the CPU IRQ priority. The system interrupt source is mapped to bit 0-15 of intrSrc parameter and CPU IRQ is mapped to bit 16-31 of intrSrc parameter.

For CM0+ core, deep Sleep wakeup-capability is determined by the CPUSS_CM0_DPSLP_IRQ_NR parameter, where the first N number of muxes (NvicMux0 ... NvicMuxN-1) have the capability to trigger Deep Sleep interrupts. A Deep Sleep capable interrupt source must be connected to one of these muxes to be able to trigger in Deep Sleep. Refer to the IRQn_Type definition in the device header.

1. For CPUSS_ver1 the CM0+ core supports up to 32 interrupt channels (IRQn 0-31). To allow all device interrupts to be routable to the NVIC of this core, there is a 240:1 multiplexer at each of the 32 NVIC channels.
2. For CPUSS_ver2 the CM0+ core supports up to 8 hardware interrupt channels (IRQn 0-7) and software-only interrupt channels (IRQn 8-15). The device has up to 1023 interrupts that can be connected to any of the hardware interrupt channels. In this structure, multiple interrupt sources can be connected simultaneously to one NVIC channel. The application must then query the interrupt source on the channel and service the active interrupt(s). The priority of these interrupts is determined by the interrupt number as defined in the cy_en_intr_t enum, where the lower number denotes higher priority over the higher number.

Enable

After initializing an interrupt, use the CMSIS Core NVIC_EnableIRQ() function to enable it. Given an initialization structure named config, the function should be called as follows:

NVIC_EnableIRQ(config.intrSrc)

Writing an interrupt service routine

Servicing interrupts in the Peripheral Drivers should follow a prescribed recipe to ensure all interrupts are serviced and duplicate interrupts are not received. Any peripheral-specific register that must be written to clear the source of the interrupt should be written as soon as possible in the interrupt service routine. However, note that due to buffering on the output bus to the peripherals, the write clearing of the interrupt may be delayed. After performing the normal interrupt service that should respond to the interrupting condition, the interrupt register that was initially written to clear the register should be read before returning from the interrupt service routine. This read ensures that the initial write has been flushed out to the hardware. Note, no additional processing should be performed based on the result of this read, as this read is intended only to ensure the write operation is flushed.

This final read may indicate a pending interrupt. What this means is that in the interval between when the write actually happened at the peripheral and when the read actually happened at the peripheral, an interrupting condition occurred. This is ok and a return from the interrupt is still the correct action. As soon as conditions warrant, meaning interrupts are enabled and there are no higher priority interrupts pending, the interrupt will be triggered again to service the additional condition.

Configuration Considerations

Certain CM0+ NVIC IRQn channels are reserved for system use:

NVIC channel (IRQn_Type)	Interrupt source (cy_en_intr_t)	Purpose
#0 (NvicMux0_IRQn)	IPC Interrupt #0 (cpuss_interrupts_ipc_0_IRQn)	System Calls to ROM
#1 (NvicMux1_IRQn)	IPC Interrupt #3 (cpuss_interrupts_ipc_3_IRQn)	System IPC pipe in the default startup

Note

For CPUSS_ver2, each NVIC channel can be shared between multiple interrupt sources. However it is not recommended to share the application NVIC channel with the reserved channels.

In CAT1C, NvicMux0_IRQn and NvicMux1_IRQn are used by ROM and not meant for user.

More Information

Refer to the technical reference manual (TRM) and the device datasheet.

Changelog

Version	Changes	Reason for Change
1.130	Updated API Cy_SysInt_SetVector for non-cacheable data check .	Code enhancement.
1.120	Updated Pre-processor checks.	Code enhancement.
1.110	Updated API Cy_SysInt_Init.	CM0P interrupt priority bug fix.
1.100	Added support for TRAVEO™ II Body Entry devices. Pre-processor check for MXS40SRSS version now groups ver. 2 with ver. 3. Previously ver. 2 was grouped with ver. 1. Added support for CM0+/CM4 dual core devices. Previously only supported CM0+/CM7 devices.	Code enhancement and support for new devices.
1.90.1	Fixed MISRA 2012 8.5 and 8.6 violations.	MISRA 2012 compliance..
1.90	Updated Cy_SysInt_Init, Cy_SysInt_SetVector and Cy_SysInt_GetVector APIs.	Code Clean up.
1.80	API's Cy_SysInt_SetInterruptSource(), Cy_SysInt_GetInterruptSource(), Cy_SysInt_DisconnectInterruptSource(), Cy_SysInt_SetNmiSource(), Cy_SysInt_GetNmiSource(), Cy_SysInt_SoftwareTrig(), Cy_SysInt_GetNvicConnection(), Cy_SysInt_GetInterruptActive(), Cy_SysInt_InitExtIRQ(), Cy_SysInt_InitIntIRQ(), Cy_SysInt_Init(), Cy_SysInt_SetVector(), Cy_SysInt_GetVector(), Cy_SysInt_SetSystemIrqVector(), Cy_SysInt_EnableSystemInt(), Cy_SysInt_DisableSystemInt() modified.	New device support, Fix Coverity issues, Documentation enhancement.
1.70	Support for CAT1C, CAT1D. Newly added API's Cy_SysInt_SetSystemIrqVector() to set the user ISR vector for the System Interrupt, Cy_SysInt_GetSystemIrqVector() to get the address of the current user ISR vector for the System Interrupt, Cy_SysInt_EnableSystemInt() to enable system interrupt, Cy_SysInt_DisableSystemInt() to disable system interrupt, Cy_SysInt_InitExtIRQ() to initialize the referenced external interrupt by setting the CPU IRQ priority and the interrupt vector, Cy_SysInt_InitIntIRQ() to initialize the referenced internal interrupt by setting the priority and the interrupt vector.	New devices support.
1.60	Support for CM33.	New devices support.
1.50	Fixed MISRA 2012 violations.	MISRA 2012 compliance.
1.40	Updated the CY_SYSINT_IS_PC_0 macro to access the protected register for the secure CYB06xx7 devices via PRA (Protected Register Access) driver.	Added PSoC 64 devices support.
1.30.1	Minor documentation updates.	Documentation enhancement.
1.30	The Cy_SysInt_SetNmiSource is updated with Protection Context check for CM0+.	User experience enhancement.
1.20.1	The Vector Table section is extended with a code snippet.	Documentation enhancement.
1.20	Flattened the organization of the driver source code into the single source directory and the single include directory.	Driver library directory-structure simplification.
	Added CPUSS_ver2 support to the following API functions: Cy_SysInt_SetInterruptSource Cy_SysInt_SetNmiSource Cy_SysInt_GetNmiSource Added new API functions: Cy_SysInt_DisconnectInterruptSource Cy_SysInt_GetNvicConnection Cy_SysInt_GetInterruptActive Deprecated following functions: Cy_SysInt_SetIntSource Cy_SysInt_GetIntSource Cy_SysInt_SetIntSourceNMI Cy_SysInt_GetIntSourceNMI	New devices support.
	Added register access layer. Use register access macros instead of direct register access using dereferenced pointers.	Makes register access device-independent, so that the PDL does not need to be recompiled for each supported part number.
1.10	Cy_SysInt_GetState() function is redefined to call NVIC_GetEnableIRQ()
1.0	Initial version

API Reference
	Macros
	Global variables
	Functions
	Data Structures
	Enumerated Types

Macros
#define	CY_SYSINT_INTRSRC_MASK   (0xFFFFUL)
	Bit 0-15 indicate system interrupt and bit 16-31 will indicate the CPU IRQ.
#define	CY_SYSINT_INTRSRC_MUXIRQ_SHIFT   (16UL)
	Bit 0-15 indicate system interrupt and bit 16-31 will indicate the CPU IRQ.