General Description

API Reference
	Status codes
	Function status type codes.

	Assert Classes and Levels
	Defines for the Assert Classes and Levels.

	Reset cause
	Define RESET_CAUSE mask values.

	Unique ID
	Unique ID fields positions.

Macros
#define	CY_CPU_CORTEX_M0P (__CORTEX_M == 0U)
	The macro for ARM CORTEX CM0P. More...

#define	CY_CPU_CORTEX_M4 (__CORTEX_M == 4U)
	The macro for ARM CORTEX CM4. More...

#define	CY_CPU_CORTEX_M7 (__CORTEX_M == 7U)
	The macro for ARM CORTEX CM7. More...

#define	CY_CPU_CORTEX_M55 (__CORTEX_M == 55U)
	The macro for ARM CORTEX CM55. More...

#define	CY_CPU_CORTEX_M33 (__CORTEX_M == 33U)
	The macro for ARM CORTEX CM33. More...

#define	CY_ARM_FAULT_DEBUG_ENABLED (1U)
	The macro to enable the Fault Handler.

#define	CY_ARM_FAULT_DEBUG (CY_ARM_FAULT_DEBUG_ENABLED)
	The macro defines if the Fault Handler is enabled. More...

#define	CY_SYSLIB_DELAY_CALIBRATION_FACTOR 1U
	This macro is to be enabled and set appropriately for the CPU's which has branch prediction enabled, so the delay can work accurately. More...

#define	CY_SYSLIB_DRV_VERSION_MAJOR 3
	The driver major version.

#define	CY_SYSLIB_DRV_VERSION_MINOR 60
	The driver minor version.

#define	CY_SECTION_RAMFUNC_BEGIN CY_SECTION(".cy_ramfunc")
	Define start of the function placed to the SRAM area by the linker.

#define	CY_SECTION_RAMFUNC_END
	Define end of the function placed to the SRAM area by the linker.

#define	CY_SECTION_SRAM1_CODE_BEGIN CY_SECTION(".cy_sram1_code")
	Define start of the function placed to the SRAM1 area by the linker.

#define	CY_SECTION_SRAM1_CODE_END
	Define end of the function placed to the SRAM1 area by the linker.

#define	CY_SECTION_SRAM1_DATANS_BEGIN CY_SECTION(".cy_sram1_data_ns")
	Define start of the function placed to the SRAM1 area by the linker.

#define	CY_SECTION_SRAM1_DATANS_END
	Define end of the function placed to the SRAM1 area by the linker.

#define	CY_SECTION_SRAM0_DATANS_BEGIN CY_SECTION(".cy_sram0_data_ns")
	Define start of the function placed to the SRAM1 area by the linker.

#define	CY_SECTION_SRAM0_DATANS_END
	Define end of the function placed to the SRAM1 area by the linker.

#define	CY_SECTION_INIT_CODECOPY_BEGIN
	Define start of the code block to be copied to SRAM by the linker during init.

#define	CY_SECTION_INIT_CODECOPY_END
	Define end of the code block to be copied to SRAM by the linker during init.

#define	CY_SECTION_SHAREDMEM CY_SECTION(".cy_sharedmem")
	Define variable to be placed to the shared SRAM area by the linker. More...

#define	CY_SECTION_SHAREDMEM_SEC CY_SECTION(".cy_sharedmem_sec")
	Define variable to be placed to the secured shared SRAM area by the linker.

#define	CY_SECTION_SOCMEMSRAMCODE_BEGIN CY_SECTION(".cy_socmem_code")
	Define start of code to be placed to the SOCMEMSRAM area by the linker.

#define	CY_SECTION_SOCMEMSRAMDATA_BEGIN CY_SECTION(".cy_socmem_data")
	Define end of code placed to the SOCMEMSRAM area by the linker. More...

#define	CY_SECTION_SOCMEMSRAMSHARED_BEGIN CY_SECTION(".cy_shared_socmem")
	Define end of code placed to the SOCMEMSRAM area by the linker. More...

#define	CY_SECTION_SRAM0DATA_BEGIN CY_SECTION(".cy_sram0_data")
	Define end of shared data to be placed to the SOCMEMSRAM area by the linker. More...

#define	CY_SECTION_SRAM0DATA_END
	Define end of the function placed to the ITCM area by the linker.

#define	CY_MAX_FILE_NAME_SIZE (24U)
	The max size of the file name which stores the ASSERT location.

#define	CY_R0_Pos (0U)
	The position of the R0 content in a fault structure.

#define	CY_R1_Pos (1U)
	The position of the R1 content in a fault structure.

#define	CY_R2_Pos (2U)
	The position of the R2 content in a fault structure.

#define	CY_R3_Pos (3U)
	The position of the R3 content in a fault structure.

#define	CY_R12_Pos (4U)
	The position of the R12 content in a fault structure.

#define	CY_LR_Pos (5U)
	The position of the LR content in a fault structure.

#define	CY_PC_Pos (6U)
	The position of the PC content in a fault structure.

#define	CY_PSR_Pos (7U)
	The position of the PSR content in a fault structure.

#define	CY_UNUSED_PARAM(a) (void)(a)
	Suppresses the unused parameter warning. More...

#define	CY_ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0]))
	Returns the size of Array. More...

#define	CY_IPC_DATA_FOR_CM4_SOFT_RESET (0x1B000002UL)
	Bit[31:24] Opcode = 0x1B (SoftReset) Bit[7:1] Type = 1 (Only CM4 reset) More...

Typedefs
typedef void(*	cy_israddress) (void)
	Type of ISR callbacks.

typedef char	char_t
	Specific-length typedef for the basic numerical types of char.

typedef float	float32_t
	Specific-length typedef for the basic numerical types of float.

typedef double	float64_t
	Specific-length typedef for the basic numerical types of double.

Variables
char_t	cy_assertFileName [CY_MAX_FILE_NAME_SIZE+1]
	The assert buffer.

uint32_t	cy_assertLine
	The assert line value.

cy_stc_fault_frame_t	cy_faultFrame
	Fault frame structure.

Macro Definition Documentation

◆ CY_CPU_CORTEX_M0P

#define CY_CPU_CORTEX_M0P (__CORTEX_M == 0U)

The macro for ARM CORTEX CM0P.

CM0+ core CPU Code

◆ CY_CPU_CORTEX_M4

#define CY_CPU_CORTEX_M4 (__CORTEX_M == 4U)

The macro for ARM CORTEX CM4.

CM4 core CPU Code

◆ CY_CPU_CORTEX_M7

#define CY_CPU_CORTEX_M7 (__CORTEX_M == 7U)

The macro for ARM CORTEX CM7.

CM7 core CPU Code

◆ CY_CPU_CORTEX_M55

#define CY_CPU_CORTEX_M55 (__CORTEX_M == 55U)

The macro for ARM CORTEX CM55.

CM55 core CPU Code

◆ CY_CPU_CORTEX_M33

#define CY_CPU_CORTEX_M33 (__CORTEX_M == 33U)

The macro for ARM CORTEX CM33.

CM33 core CPU Code

◆ CY_ARM_FAULT_DEBUG

#define CY_ARM_FAULT_DEBUG (CY_ARM_FAULT_DEBUG_ENABLED)

The macro defines if the Fault Handler is enabled.

Enabled by default.

◆ CY_SYSLIB_DELAY_CALIBRATION_FACTOR

#define CY_SYSLIB_DELAY_CALIBRATION_FACTOR 1U

This macro is to be enabled and set appropriately for the CPU's which has branch prediction enabled, so the delay can work accurately.

CY_SYSLIB_DELAY_CALIBRATION_FACTOR = 1 for CM0P, CM33 and CM4. CY_SYSLIB_DELAY_CALIBRATION_FACTOR = 2 for CM7_0 and CM7_1.

◆ CY_SECTION_SHAREDMEM

#define CY_SECTION_SHAREDMEM CY_SECTION(".cy_sharedmem")

Define variable to be placed to the shared SRAM area by the linker.

This memory region is un-cached for CM55 core

◆ CY_SECTION_SOCMEMSRAMDATA_BEGIN

#define CY_SECTION_SOCMEMSRAMDATA_BEGIN CY_SECTION(".cy_socmem_data")

Define end of code placed to the SOCMEMSRAM area by the linker.

Define start of data to be placed to the SOCMEMSRAM area by the linker

◆ CY_SECTION_SOCMEMSRAMSHARED_BEGIN

#define CY_SECTION_SOCMEMSRAMSHARED_BEGIN CY_SECTION(".cy_shared_socmem")

Define end of code placed to the SOCMEMSRAM area by the linker.

Define start of shared data to be placed to the SOCMEMSRAM area by the linker. This memory region is un-cached for CM55 core

◆ CY_SECTION_SRAM0DATA_BEGIN

#define CY_SECTION_SRAM0DATA_BEGIN CY_SECTION(".cy_sram0_data")

Define end of shared data to be placed to the SOCMEMSRAM area by the linker.

Define start of function placed to the bootstrap area by the linker Define end of function placed to the bootstrap area by the linker Placed initialized global variable to the bootstrap data area by the linker Placed un-init global variable to the bootstrap bss area by the linker Define start of the data placed in the SRAM0 area by the linker

◆ CY_UNUSED_PARAM

#define CY_UNUSED_PARAM ( a ) (void)(a)

Suppresses the unused parameter warning.

Note: This macro is available for devices having M33SYSCPUSS IP.

◆ CY_ARRAY_SIZE

#define CY_ARRAY_SIZE ( x ) (sizeof(x) / sizeof((x)[0]))

Returns the size of Array.

Parameters

x	Array Name

Note: This macro is available for devices having M33SYSCPUSS IP.

◆ CY_IPC_DATA_FOR_CM4_SOFT_RESET

#define CY_IPC_DATA_FOR_CM4_SOFT_RESET (0x1B000002UL)

Bit[31:24] Opcode = 0x1B (SoftReset) Bit[7:1] Type = 1 (Only CM4 reset)

Note: This macro is available for devices having M4CPUSS IP.