Functions

General Description

Functions
cy_en_sysclk_status_t	Cy_SysClk_PllConfigure (uint32_t clkPath, const cy_stc_pll_config_t *config)
	Configures a given PLL. More...
cy_en_sysclk_status_t	Cy_SysClk_PllManualConfigure (uint32_t clkPath, const cy_stc_pll_manual_config_t *config)
	Manually configures a PLL based on user inputs. More...
cy_en_sysclk_status_t	Cy_SysClk_PllGetConfiguration (uint32_t clkPath, cy_stc_pll_manual_config_t *config)
	Reports configuration settings for a PLL. More...
cy_en_sysclk_status_t	Cy_SysClk_PllEnable (uint32_t clkPath, uint32_t timeoutus)
	Enables the PLL. More...
__STATIC_INLINE bool	Cy_SysClk_PllLocked (uint32_t clkPath)
	Reports whether or not the selected PLL is locked. More...
__STATIC_INLINE bool	Cy_SysClk_PllIsEnabled (uint32_t clkPath)
	Reports whether or not the selected PLL is enabled. More...
__STATIC_INLINE bool	Cy_SysClk_PllLostLock (uint32_t clkPath)
	Reports whether or not the selected PLL lost its lock since the last time this function was called. More...
__STATIC_INLINE cy_en_sysclk_status_t	Cy_SysClk_PllDisable (uint32_t clkPath)
	Disables the selected PLL. More...

Function Documentation

Cy_SysClk_PllConfigure()

cy_en_sysclk_status_t Cy_SysClk_PllConfigure	(	uint32_t	clkPath,
		const cy_stc_pll_config_t *	config
	)

Configures a given PLL.

The configuration formula used is: Fout = pll_clk * (P / Q / div_out), where: Fout is the desired output frequency pll_clk is the frequency of the input source P is the feedback divider. Its value is in bitfield FEEDBACK_DIV. Q is the reference divider. Its value is in bitfield REFERENCE_DIV. div_out is the reference divider. Its value is in bitfield OUTPUT_DIV.

Parameters

clkPath	Selects which PLL to configure. 1 is the first PLL; 0 is invalid.
config	cy_stc_pll_config_t

Returns

Error / status code:
CY_SYSCLK_SUCCESS - PLL successfully configured
CY_SYSCLK_INVALID_STATE - PLL not configured because it is enabled
CY_SYSCLK_BAD_PARAM - Invalid clock path number, or input or desired output frequency is out of valid range

Note

Call this function after changing the PLL input frequency, for example if Cy_SysClk_ClkPathSetSource() is called.

Do not call this function when the PLL is enabled. If it is called, then this function returns immediately with an error return value and no register updates.

Call SystemCoreClockUpdate after this function calling if it affects the CLK_HF0 frequency.

Call Cy_SysLib_SetWaitStates before calling this function if the PLL is the source of CLK_HF0 and the PLL frequency is increasing.

Call Cy_SysLib_SetWaitStates after calling this function if the PLL is the source of CLK_HF0 and the PLL frequency is decreasing.

On PSoC 64 devices the configuration on the PRA driver will be reflected after Cy_SysClk_PllEnable call. Any call to Cy_SysClk_PllGetConfiguration before calling Cy_SysClk_PllEnable returns old configuration values.

Function Usage

    /* Scenario: PLL needs to source HFCLK0, which must operate at 100 MHz.
                 The IMO sources the PLL at 8MHz. Startup time is not an issue
                 and manual configuration of the PLL is not needed. */

    cy_stc_pll_config_t pllConfig =
    {
        /*.inputFreq  =*/ 8000000UL,                    /* PLL input: 8 MHz IMO */
        /*.outputFreq =*/ 100000000UL,                  /* PLL output: 100 MHz */
        /*.lfMode     =*/ true,                         /* Enable low frequency mode (VCO = 170~200 MHz) */
        /*.outputMode =*/ CY_SYSCLK_FLLPLL_OUTPUT_AUTO  /* Output 100 MHz when locked. Otherwise 8 MHz */
    };

    /* Set the PLL source (path 1 mux) to be the IMO.
       Note: Path 0 is not valid for PLL. */
    (void)Cy_SysClk_ClkPathSetSource(1UL, CY_SYSCLK_CLKPATH_IN_IMO);

    /* Configure Path 1 PLL with the settings in pllConfig struct */
    if (CY_SYSCLK_SUCCESS != Cy_SysClk_PllConfigure(1UL, &pllConfig))
    {
        /* Insert error handling */
    }

    /* Enable the Path 1 PLL with 2000 microsecond timeout */
    if (CY_SYSCLK_SUCCESS != Cy_SysClk_PllEnable(1UL, 2000UL))
    {
        /* Insert error handling */
    }

    /* Set the HFCLK0 source to clock path 1 */
    (void)Cy_SysClk_ClkHfSetSource(0UL, CY_SYSCLK_CLKHF_IN_CLKPATH1);

Cy_SysClk_PllManualConfigure()

cy_en_sysclk_status_t Cy_SysClk_PllManualConfigure	(	uint32_t	clkPath,
		const cy_stc_pll_manual_config_t *	config
	)

Manually configures a PLL based on user inputs.

Parameters

clkPath	Selects which PLL to configure. 1 is the first PLL; 0 is invalid.
config	cy_stc_pll_manual_config_t

Returns

Error / status code:
CY_SYSCLK_SUCCESS - PLL successfully configured
CY_SYSCLK_INVALID_STATE - PLL not configured because it is enabled
CY_SYSCLK_BAD_PARAM - invalid clock path number CY_SYSCLK_INVALID_STATE - ECO already enabled For the PSoC 64 devices there are possible situations when function returns the PRA error status code. This is because for PSoC 64 devices the function uses the PRA driver to change the protected registers. Refer to cy_en_pra_status_t for more details.

Note

Call this function after changing the PLL input frequency; for example if Cy_SysClk_ClkPathSetSource() is called.

Do not call this function when the PLL is enabled. If it is called, then this function returns immediately with an error return value and no register updates.

Call SystemCoreClockUpdate after this function calling if it affects the CLK_HF0 frequency.

Call Cy_SysLib_SetWaitStates before calling this function if the PLL is the source of CLK_HF0 and the PLL frequency is increasing.

Call Cy_SysLib_SetWaitStates after calling this function if the PLL is the source of CLK_HF0 and the PLL frequency is decreasing.

On PSoC 64 devices the configuration on the PRA driver will be reflected after Cy_SysClk_PllEnable call. Any call to Cy_SysClk_PllGetConfiguration before calling Cy_SysClk_PllEnable returns old configuration values.

Function Usage

    /* Scenario: PLL needs to source HFCLK0, which must operate at 100 MHz.
                 The IMO sources the PLL at 8MHz. The characteristics of the
                 PLL lock parameters are already known and the startup time
                 for the PLL configuration must be minimized. */

    /* Refer to the TRM for the full set of equations used to calculate the parameters */
    cy_stc_pll_manual_config_t pllConfig =
    {
        /*.feedbackDiv  =*/ 25u,                            /* Feedback divider */
        /*.referenceDiv =*/ 1u,                             /* Reference divider */
        /*.outputDiv    =*/ 2u,                             /* Output divider */
        /*.lfMode       =*/ true,                           /* Enable low frequency mode (VCO = 170~200 MHz) */
        /*.outputMode   =*/ CY_SYSCLK_FLLPLL_OUTPUT_AUTO    /* Output 100 MHz when locked. Otherwise 8 MHz */
    };

    /* Set the PLL source (path 1 mux) to be the IMO.
       Note: Path 0 is not valid for PLL. */
    (void)Cy_SysClk_ClkPathSetSource(1UL, CY_SYSCLK_CLKPATH_IN_IMO);

    /* Configure Path 1 PLL with the settings in pllConfig struct */
    if (CY_SYSCLK_SUCCESS != Cy_SysClk_PllManualConfigure(1UL, &pllConfig))
    {
        /* Insert error handling */
    }

    /* Enable the path 1 PLL with 2000 microsecond timeout */
    if (CY_SYSCLK_SUCCESS != Cy_SysClk_PllEnable(1UL, 2000UL))
    {
        /* Insert error handling */
    }

    /* Set the HFCLK0 source to clock path 1 */
    (void)Cy_SysClk_ClkHfSetSource(0UL, CY_SYSCLK_CLKHF_IN_CLKPATH1);

Cy_SysClk_PllGetConfiguration()

cy_en_sysclk_status_t Cy_SysClk_PllGetConfiguration	(	uint32_t	clkPath,
		cy_stc_pll_manual_config_t *	config
	)

Reports configuration settings for a PLL.

Parameters

clkPath	Selects which PLL to report. 1 is the first PLL; 0 is invalid.
config	cy_stc_pll_manual_config_t

Returns

Error / status code:
CY_SYSCLK_SUCCESS - PLL data successfully reported
CY_SYSCLK_BAD_PARAM - invalid clock path number CY_SYSCLK_INVALID_STATE - ECO already enabled For the PSoC 64 devices there are possible situations when function returns the PRA error status code. This is because for PSoC 64 devices the function uses the PRA driver to change the protected registers. Refer to cy_en_pra_status_t for more details.

Note

On PSoC 64 devices the configuration on the PRA driver will be reflected after Cy_SysClk_PllEnable call. Any call to Cy_SysClk_PllGetConfiguration before calling Cy_SysClk_PllEnable returns old configuration values.

Function Usage

    /* Scenario: The calculated PLL parameters need to be checked. */

    cy_stc_pll_config_t autoPllConfig =
    {
        /*.inputFreq  =*/ 8000000UL,                    /* PLL input: 8 MHz IMO */
        /*.outputFreq =*/ 100000000UL,                  /* PLL output: 100 MHz */
        /*.lfMode     =*/ true,                         /* Enable low frequency mode (VCO = 170~200 MHz) */
        /*.outputMode =*/ CY_SYSCLK_FLLPLL_OUTPUT_AUTO  /* Output 100 MHz when locked. Otherwise 8 MHz */
    };

    cy_stc_pll_manual_config_t getPllParams;

    /* Configure Path 1 PLL with the settings in pllConfig struct */
    if (CY_SYSCLK_SUCCESS != Cy_SysClk_PllConfigure(1UL, &autoPllConfig))
    {
        /* Insert error handling */
    }

    /* Retrieve the calculated parameters of Path 1 PLL */
    (void)Cy_SysClk_PllGetConfiguration(1UL, &getPllParams);

Cy_SysClk_PllEnable()

cy_en_sysclk_status_t Cy_SysClk_PllEnable	(	uint32_t	clkPath,
		uint32_t	timeoutus
	)

Enables the PLL.

The PLL should be configured before calling this function.

Parameters

clkPath	Selects which PLL to enable. 1 is the first PLL; 0 is invalid.
timeoutus	amount of time in microseconds to wait for the PLL to lock. If the lock doesn't occur, PLL is stopped. To avoid waiting for lock, set this to 0 and manually check for lock using Cy_SysClk_PllLocked.

Returns

Error / status code:
CY_SYSCLK_SUCCESS - PLL successfully enabled
CY_SYSCLK_TIMEOUT - Timeout waiting for PLL lock
CY_SYSCLK_BAD_PARAM - invalid clock path number CY_SYSCLK_INVALID_STATE - ECO already enabled For the PSoC 64 devices there are possible situations when function returns the PRA error status code. This is because for PSoC 64 devices the function uses the PRA driver to change the protected registers. Refer to cy_en_pra_status_t for more details.

Note

Call SystemCoreClockUpdate after this function calling if it affects the CLK_HF0 frequency.

Call Cy_SysLib_SetWaitStates before calling this function if the PLL is the source of CLK_HF0 and the CLK_HF0 frequency is increasing.

Call Cy_SysLib_SetWaitStates after calling this function if the PLL is the source of CLK_HF0 and the CLK_HF0 frequency is decreasing.

Function Usage

    /* Scenario: PLL is configured and needs to be enabled within 2 ms */

    /* Enable the Path 1 PLL with a timeout of 2000 microsecond */
    if (CY_SYSCLK_SUCCESS != Cy_SysClk_PllEnable(1UL, 2000UL))
    {
        /* Insert error handling */
    }

Cy_SysClk_PllLocked()

__STATIC_INLINE bool Cy_SysClk_PllLocked

(

uint32_t

clkPath

)

Reports whether or not the selected PLL is locked.

Parameters

clkPath

Selects which PLL to check. 1 is the first PLL; 0 is invalid.

Returns

false = not locked
true = locked

Function Usage

    /* Scenario: PLL is configured and needs to be enabled in a non-blocking way */

    /* Enable the Path 1 PLL without timeout */
    (void)Cy_SysClk_PllEnable(1UL, 0UL);

    /* Check the status of the lock */
    while(Cy_SysClk_PllLocked(1UL))
    {
        /* Perform other actions while the PLL is locking */
    }

    /* PLL Locked. Proceed with further configuration */

Cy_SysClk_PllIsEnabled()

__STATIC_INLINE bool Cy_SysClk_PllIsEnabled

(

uint32_t

clkPath

)

Reports whether or not the selected PLL is enabled.

Parameters

clkPath

Selects which PLL to check. 1 is the first PLL; 0 is invalid.

Returns

false = disabled
true = enabled

Function Usage

    /* Scenario: Path 1 PLL failed to enable and must be reconfigured. Or the
                 PLL is no longer used and hence needs to be disabled. */

    if (Cy_SysClk_PllIsEnabled(1UL))
    {
        if (CY_SYSCLK_SUCCESS != Cy_SysClk_PllDisable(1UL))
        {
            /* Insert error handling */
        }
    }

    /* The clocks that relied on the PLL will now run off of the clock that
       was used to source the FLL (e.g. IMO or ECO). */

Cy_SysClk_PllLostLock()

__STATIC_INLINE bool Cy_SysClk_PllLostLock

(

uint32_t

clkPath

)

Reports whether or not the selected PLL lost its lock since the last time this function was called.

Clears the lost lock indicator.

Parameters

clkPath

Selects which PLL to check. 1 is the first PLL; 0 is invalid.

Returns

false = did not lose lock
true = lost lock

Function Usage

    /* Scenario: Suspicious change in Path 1 clock frequency was encountered
                 in the application. Check if the Path 1 PLL lost the lock. */

    if(Cy_SysClk_PllLostLock(1UL))
    {
        /* Insert error handling */
    }

Cy_SysClk_PllDisable()

__STATIC_INLINE cy_en_sysclk_status_t Cy_SysClk_PllDisable

(

uint32_t

clkPath

)

Disables the selected PLL.

Parameters

clkPath

Selects which PLL to disable. 1 is the first PLL; 0 is invalid.

Returns

Error / status code:
CY_SYSCLK_SUCCESS - PLL successfully disabled
CY_SYSCLK_BAD_PARAM - invalid clock path number CY_SYSCLK_INVALID_STATE - ECO already enabled For the PSoC 64 devices there are possible situations when function returns the PRA error status code. This is because for PSoC 64 devices the function uses the PRA driver to change the protected registers. Refer to cy_en_pra_status_t for more details.

Note

Call SystemCoreClockUpdate after this function calling if it affects the CLK_HF0 frequency.

Call Cy_SysLib_SetWaitStates before calling this function if the PLL is the source of CLK_HF0 and the CLK_HF0 frequency is increasing.

Call Cy_SysLib_SetWaitStates after calling this function if the PLL is the source of CLK_HF0 and the CLK_HF0 frequency is decreasing.

Function Usage

    /* Scenario: Path 1 PLL failed to enable and must be reconfigured. Or the
                 PLL is no longer used and hence needs to be disabled. */

    if (Cy_SysClk_PllIsEnabled(1UL))
    {
        if (CY_SYSCLK_SUCCESS != Cy_SysClk_PllDisable(1UL))
        {
            /* Insert error handling */
        }
    }

    /* The clocks that relied on the PLL will now run off of the clock that
       was used to source the FLL (e.g. IMO or ECO). */