PSoC 6 Peripheral Driver Library

General Description

Functions

__STATIC_INLINE cy_en_sysclk_status_t Cy_SysClk_ClkHfEnable (uint32_t clkHf)
 Enables the selected clkHf. More...
 
__STATIC_INLINE bool Cy_SysClk_ClkHfIsEnabled (uint32_t clkHf)
 Reports the Enabled/Disabled status of clkHf. More...
 
__STATIC_INLINE cy_en_sysclk_status_t Cy_SysClk_ClkHfDisable (uint32_t clkHf)
 Disables the selected clkHf. More...
 
__STATIC_INLINE cy_en_sysclk_status_t Cy_SysClk_ClkHfSetSource (uint32_t clkHf, cy_en_clkhf_in_sources_t source)
 Selects the source of the selected clkHf. More...
 
__STATIC_INLINE cy_en_clkhf_in_sources_t Cy_SysClk_ClkHfGetSource (uint32_t clkHf)
 Reports the source of the selected clkHf. More...
 
__STATIC_INLINE cy_en_sysclk_status_t Cy_SysClk_ClkHfSetDivider (uint32_t clkHf, cy_en_clkhf_dividers_t divider)
 Sets the pre-divider for a clkHf. More...
 
__STATIC_INLINE cy_en_clkhf_dividers_t Cy_SysClk_ClkHfGetDivider (uint32_t clkHf)
 Reports the pre-divider value for a clkHf. More...
 
uint32_t Cy_SysClk_ClkHfGetFrequency (uint32_t clkHf)
 Reports the frequency of the selected clkHf. More...
 

Function Documentation

◆ Cy_SysClk_ClkHfEnable()

__STATIC_INLINE cy_en_sysclk_status_t Cy_SysClk_ClkHfEnable ( uint32_t  clkHf)

Enables the selected clkHf.

Parameters
clkHfSelects which clkHf to enable.
Returns
cy_en_sysclk_status_t CY_SYSCLK_INVALID_STATE - ECO already enabled For the PSoC 64 devices there are possible situations when function returns the PRA error status code. This is because for PSoC 64 devices the function uses the PRA driver to change the protected registers. Refer to cy_en_pra_status_t for more details.
Function Usage
/* Scenario: ECO needs to source HFCLK2 through Path 2. The ECO is
configured through its function calls. */
#define CLKPATH2 (2UL)
#define HFCLK2 (2UL)
uint32_t clkPathMuxFreq = 0UL; /* Variable to store the Clock Path Mux output frequency */
/* Set the clock path 2 mux to be sourced from ECO */
{
clkPathMuxFreq = Cy_SysClk_ClkPathMuxGetFrequency(CLKPATH2);
/* Now clkPathMuxFreq contains the Clock Path Mux output frequency */
}
else
{
/* Perform error handling */
}
/* Set the HFCLK2 source to clock path 2 and enable HFCLK2 */
/* Enable HFCLK2 */
(void)Cy_SysClk_ClkHfEnable(HFCLK2);

◆ Cy_SysClk_ClkHfIsEnabled()

__STATIC_INLINE bool Cy_SysClk_ClkHfIsEnabled ( uint32_t  clkHf)

Reports the Enabled/Disabled status of clkHf.

Parameters
clkHfSelects which clkHf to check.
Returns
Boolean status of clkHf: true - Enabled, false - Disabled.
Function Usage
/* Scenario: HFCLK1 is no longer required in the application and can be
switched off.
Note: HFCLK0 cannot be disabled */
#define HFCLK1 (1UL)
{
/* Disable HFCLK1 */
(void)Cy_SysClk_ClkHfDisable(HFCLK1);
}

◆ Cy_SysClk_ClkHfDisable()

__STATIC_INLINE cy_en_sysclk_status_t Cy_SysClk_ClkHfDisable ( uint32_t  clkHf)

Disables the selected clkHf.

Parameters
clkHfSelects which clkHf to enable.
Returns
cy_en_sysclk_status_t
Note
clkHf[0] cannot be disabled.
Function Usage
/* Scenario: HFCLK1 is no longer required in the application and can be
switched off.
Note: HFCLK0 cannot be disabled */
#define HFCLK1 (1UL)
{
/* Disable HFCLK1 */
(void)Cy_SysClk_ClkHfDisable(HFCLK1);
}

◆ Cy_SysClk_ClkHfSetSource()

__STATIC_INLINE cy_en_sysclk_status_t Cy_SysClk_ClkHfSetSource ( uint32_t  clkHf,
cy_en_clkhf_in_sources_t  source 
)

Selects the source of the selected clkHf.

Parameters
clkHfselects which clkHf mux to configure.
sourcecy_en_clkhf_in_sources_t
Returns
cy_en_sysclk_status_t CY_SYSCLK_INVALID_STATE - ECO already enabled For the PSoC 64 devices there are possible situations when function returns the PRA error status code. This is because for PSoC 64 devices the function uses the PRA driver to change the protected registers. Refer to cy_en_pra_status_t for more details.
Note
Call SystemCoreClockUpdate after this function calling if it affects the CLK_HF0 frequency.
Call Cy_SysLib_SetWaitStates before calling this function if CLK_HF0 frequency is increasing.
Call Cy_SysLib_SetWaitStates after calling this function if CLK_HF0 frequency is decreasing.
Function Usage
/* Scenario: HFCLK1 source may have been updated to Path 0 somewhere in the
application. Check if it was and change the source to Path 1. */
{
/* Set the HFCLK1 source to Path 1 clock */
}

◆ Cy_SysClk_ClkHfGetSource()

__STATIC_INLINE cy_en_clkhf_in_sources_t Cy_SysClk_ClkHfGetSource ( uint32_t  clkHf)

Reports the source of the selected clkHf.

Parameters
clkHfselects which clkHf to get the source of.
Returns
cy_en_clkhf_in_sources_t
Function Usage
/* Scenario: HFCLK1 source may have been updated to Path 0 somewhere in the
application. Check if it was and change the source to Path 1. */
{
/* Set the HFCLK1 source to Path 1 clock */
}

◆ Cy_SysClk_ClkHfSetDivider()

__STATIC_INLINE cy_en_sysclk_status_t Cy_SysClk_ClkHfSetDivider ( uint32_t  clkHf,
cy_en_clkhf_dividers_t  divider 
)

Sets the pre-divider for a clkHf.

Parameters
clkHfselects which clkHf divider to configure.
dividercy_en_clkhf_dividers_t
Returns
cy_en_sysclk_status_t CY_SYSCLK_INVALID_STATE - ECO already enabled For the PSoC 64 devices there are possible situations when function returns the PRA error status code. This is because for PSoC 64 devices the function uses the PRA driver to change the protected registers. Refer to cy_en_pra_status_t for more details.
Note
Also call Cy_SysClk_ClkHfSetSource to set the clkHf source.
Call SystemCoreClockUpdate after this function calling if it affects the CLK_HF0 frequency.
Call Cy_SysLib_SetWaitStates before calling this function if CLK_HF0 frequency is increasing.
Call Cy_SysLib_SetWaitStates after calling this function if CLK_HF0 frequency is decreasing.
Function Usage
/* Scenario: Set HFCLK0 divider to 8, to reduce frequency and save power */
{
/* Set the HFCLK0 divider to 8 */
}
/* Check the HFCLK0 frequency */
uint32_t clkHf0freq = Cy_SysClk_ClkHfGetFrequency(0UL);

◆ Cy_SysClk_ClkHfGetDivider()

__STATIC_INLINE cy_en_clkhf_dividers_t Cy_SysClk_ClkHfGetDivider ( uint32_t  clkHf)

Reports the pre-divider value for a clkHf.

Parameters
clkHfselects which clkHf to check divider of.
Returns
cy_en_clkhf_dividers_t
Function Usage
/* Scenario: Set HFCLK0 divider to 8, to reduce frequency and save power */
{
/* Set the HFCLK0 divider to 8 */
}
/* Check the HFCLK0 frequency */
uint32_t clkHf0freq = Cy_SysClk_ClkHfGetFrequency(0UL);

◆ Cy_SysClk_ClkHfGetFrequency()

uint32_t Cy_SysClk_ClkHfGetFrequency ( uint32_t  clkHf)

Reports the frequency of the selected clkHf.

Parameters
clkHfSelects the clkHf
Returns
The frequency, in Hz.
Note
The reported frequency may be zero, which indicates unknown. This happens if the source input is dsi_out or clk_altlf.
Function Usage
/* Scenario: Set HFCLK0 divider to 8, to reduce frequency and save power */
{
/* Set the HFCLK0 divider to 8 */
}
/* Check the HFCLK0 frequency */
uint32_t clkHf0freq = Cy_SysClk_ClkHfGetFrequency(0UL);