SFDP Macros

General Description

Macros
#define	CY_SMIF_SFDP_ADDRESS_LENGTH   (0x03U)
	The length of the SFDP address.
#define	CY_SMIF_SFDP_PARAM_HEADER_LENGTH   (0x8U)
	The length of the Parameter header.
#define	CY_SMIF_SFDP_PARAMETER_TABLE_LENGTH   (0x64U)
	The length of the Parameter table.
#define	CY_SMIF_SFDP_LENGTH   (CY_SMIF_SFDP_PARAMETER_TABLE_LENGTH)
	The length of the SFDP.
#define	CY_SMIF_SFDP_SIGNATURE_BYTE_00   (0x00U)
	The SFDP Signature byte 0x00. More...
#define	CY_SMIF_SFDP_SIGNATURE_BYTE_01   (0x01U)
	The SFDP Signature byte 0x01. More...
#define	CY_SMIF_SFDP_SIGNATURE_BYTE_02   (0x02U)
	The SFDP Signature byte 0x02. More...
#define	CY_SMIF_SFDP_SIGNATURE_BYTE_03   (0x03U)
	The SFDP Signature byte 0x03. More...
#define	CY_SMIF_SFDP_MINOR_REV   (0x04U)
	The SFDP Header byte 0x04. More...
#define	CY_SMIF_SFDP_MAJOR_REV   (0x05U)
	The SFDP Header byte 0x05. More...
#define	CY_SMIF_SFDP_MAJOR_REV_1   (0x01U)
	The SFDP Major Revision is 1.
#define	CY_SMIF_SFDP_JEDEC_REV_B   (0x06U)
	The JEDEC JESD216 Revision is B.
#define	CY_SMIF_SFDP_PARAM_TABLE_PTR   (0x0CU)
	Specifies the start of the JEDEC Basic Flash Parameter Table in the SFDP structure.
#define	CY_SMIF_SFDP_THREE_BYTES_ADDR_CODE   (0x00U)
	Code for the SFDP Address Bytes Number 3.
#define	CY_SMIF_SFDP_THREE_OR_FOUR_BYTES_ADDR_CODE   (0x01U)
	Code for the SFDP Address Bytes Number 3 or 4.
#define	CY_SMIF_SFDP_FOUR_BYTES_ADDR_CODE   (0x02U)
	Code for the SFDP Address Bytes Number 4.
#define	CY_SMIF_THREE_BYTES_ADDR   (0x03U)
	The address Bytes Number is 3.
#define	CY_SMIF_FOUR_BYTES_ADDR   (0x04U)
	The address Bytes Number is 4.
#define	CY_SMIF_READ_MODE_BYTE   (0x5AU)
	The mode byte for the SMIF read.
#define	CY_SMIF_WRITE_STATUS_REG1_CMD   (0x01U)
	The write status register 1 command.
#define	CY_SMIF_SINGLE_PROGRAM_CMD   (0x02U)
	The command for a single SMIF program.
#define	CY_SMIF_SINGLE_READ_CMD   (0x03U)
	The command for a single SMIF read.
#define	CY_SMIF_WRITE_DISABLE_CMD   (0x04U)
	The Write Disable command.
#define	CY_SMIF_READ_STATUS_REG1_CMD   (0x05U)
	The read status register 1 command.
#define	CY_SMIF_WRITE_ENABLE_CMD   (0x06U)
	The Write Enable command.
#define	CY_SMIF_READ_STATUS_REG2_T1_CMD   (0x35U)
	The read status register 2 type 1 command.
#define	CY_SMIF_WRITE_STATUS_REG2_CMD   (0x3EU)
	The write status register 2 command.
#define	CY_SMIF_READ_STATUS_REG2_T2_CMD   (0x3FU)
	The read status register 2 type 2 command.
#define	CY_SMIF_CHIP_ERASE_CMD   (0x60U)
	The Chip Erase command.
#define	CY_SMIF_QE_BIT_STATUS_REG2_T1   (0x02U)
	The QE bit is in status register 2 type 1. More...
#define	CY_SMIF_FAST_READ_4_BYTES_CMD_1S_1S_1S   (0x0CU)
	The command for a 1S-1S-1S SMIF fast read with 4-byte addressing.
#define	CY_SMIF_FAST_READ_4_BYTES_CMD_1S_1S_2S   (0x3CU)
	The command for a 1S-1S-2S SMIF fast read with 4-byte addressing.
#define	CY_SMIF_FAST_READ_4_BYTES_CMD_1S_2S_2S   (0xBCU)
	The command for a 1S-2S-2S SMIF fast read with 4-byte addressing.
#define	CY_SMIF_FAST_READ_4_BYTES_CMD_1S_1S_4S   (0x6CU)
	The command for a 1S-1S-4S SMIF fast read with 4-byte addressing.
#define	CY_SMIF_FAST_READ_4_BYTES_CMD_1S_4S_4S   (0xECU)
	The command for a 1S-4S-4S SMIF fast read with 4-byte addressing.
#define	CY_SMIF_PAGE_PROGRAM_4_BYTES_CMD_1S_1S_1S   (0x12U)
	The command for a 1S-1S-1S SMIF page program with 4-byte addressing.
#define	CY_SMIF_PAGE_PROGRAM_4_BYTES_CMD_1S_1S_4S   (0x34U)
	The command for a 1S-1S-4S SMIF page program with 4-byte addressing.
#define	CY_SMIF_PAGE_PROGRAM_4_BYTES_CMD_1S_4S_4S   (0x3EU)
	The command for a 1S-4S-4S SMIF page program with 4-byte addressing.
#define	CY_SMIF_BRWR_EXTADD_MASK   (0x80U)
	The Extended Address Enable (EXTADD) mask.
#define	CY_SMIF_SFDP_ERASE_TIME_1MS   (1U)
	Units of Erase Typical Time in ms.
#define	CY_SMIF_SFDP_ERASE_TIME_16MS   (16U)
	Units of Erase Typical Time in ms.
#define	CY_SMIF_SFDP_ERASE_TIME_128MS   (128U)
	Units of Erase Typical Time in ms.
#define	CY_SMIF_SFDP_ERASE_TIME_1S   (1000U)
	Units of Erase Typical Time in ms.
#define	CY_SMIF_SFDP_CHIP_ERASE_TIME_16MS   (16U)
	Units of Chip Erase Typical Time in ms.
#define	CY_SMIF_SFDP_CHIP_ERASE_TIME_256MS   (256U)
	Units of Chip Erase Typical Time in ms.
#define	CY_SMIF_SFDP_CHIP_ERASE_TIME_4S   (4000U)
	Units of Chip Erase Typical Time in ms.
#define	CY_SMIF_SFDP_CHIP_ERASE_TIME_64S   (64000U)
	Units of Chip Erase Typical Time in ms.
#define	CY_SMIF_SFDP_PROG_TIME_8US   (8U)
	Units of Page Program Typical Time in us.
#define	CY_SMIF_SFDP_PROG_TIME_64US   (64U)
	Units of Page Program Typical Time in us.
#define	CY_SMIF_SFDP_UNIT_0   (0U)
	Units of Basic Flash Parameter Table Time Parameters.
#define	CY_SMIF_SFDP_UNIT_1   (1U)
	Units of Basic Flash Parameter Table Time Parameters.
#define	CY_SMIF_SFDP_UNIT_2   (2U)
	Units of Basic Flash Parameter Table Time Parameters.
#define	CY_SMIF_SFDP_UNIT_3   (3U)
	Units of Basic Flash Parameter Table Time Parameters.
#define	CY_SMIF_STATUS_REG_BUSY_MASK   (0x01U)
	The busy mask for the status registers.
#define	CY_SMIF_NO_COMMAND_OR_MODE   (0xFFFFFFFFUL)
	No command or mode present.
#define	CY_SMIF_SFDP_QER_0   (0x00UL)
	The quad Enable Requirements case 0.
#define	CY_SMIF_SFDP_QER_1   (0x01UL)
	The quad Enable Requirements case 1.
#define	CY_SMIF_SFDP_QER_2   (0x02UL)
	The quad Enable Requirements case 2.
#define	CY_SMIF_SFDP_QER_3   (0x03UL)
	The quad Enable Requirements case 3.
#define	CY_SMIF_SFDP_QER_4   (0x04UL)
	The quad Enable Requirements case 4.
#define	CY_SMIF_SFDP_QER_5   (0x05UL)
	The quad Enable Requirements case 5.
#define	CY_SMIF_SFDP_QE_BIT_1_OF_SR_2   (0x02UL)
	The QE is bit 1 of the status register 2.
#define	CY_SMIF_SFDP_QE_BIT_6_OF_SR_1   (0x40UL)
	The QE is bit 6 of the status register 1.
#define	CY_SMIF_SFDP_QE_BIT_7_OF_SR_2   (0x80UL)
	The QE is bit 7 of the status register 2.
#define	CY_SMIF_SFDP_BFPT_BYTE_02   (0x02U)
	The byte 0x02 of the JEDEC Basic Flash Parameter Table.
#define	CY_SMIF_SFDP_BFPT_BYTE_04   (0x04U)
	The byte 0x04 of the JEDEC Basic Flash Parameter Table.
#define	CY_SMIF_SFDP_BFPT_BYTE_05   (0x05U)
	The byte 0x05 of the JEDEC Basic Flash Parameter Table.
#define	CY_SMIF_SFDP_BFPT_BYTE_06   (0x06U)
	The byte 0x06 of the JEDEC Basic Flash Parameter Table: number of Parameter Headers (zero based, 05h = 6 parameters)
#define	CY_SMIF_SFDP_BFPT_BYTE_08   (0x08U)
	The byte 0x08 of the JEDEC Basic Flash Parameter Table.
#define	CY_SMIF_SFDP_BFPT_BYTE_09   (0x09U)
	The byte 0x09 of the JEDEC Basic Flash Parameter Table.
#define	CY_SMIF_SFDP_BFPT_BYTE_0A   (0x0AU)
	The byte 0x0A of the JEDEC Basic Flash Parameter Table.
#define	CY_SMIF_SFDP_BFPT_BYTE_0B   (0x0BU)
	The byte 0x0B of the JEDEC Basic Flash Parameter Table.
#define	CY_SMIF_SFDP_BFPT_BYTE_0C   (0x0CU)
	The byte 0x0C of the JEDEC Basic Flash Parameter Table.
#define	CY_SMIF_SFDP_BFPT_BYTE_0D   (0x0DU)
	The byte 0x0D of the JEDEC Basic Flash Parameter Table.
#define	CY_SMIF_SFDP_BFPT_BYTE_0E   (0x0EU)
	The byte 0x0E of the JEDEC Basic Flash Parameter Table.
#define	CY_SMIF_SFDP_BFPT_BYTE_0F   (0x0FU)
	The byte 0x0F of the JEDEC Basic Flash Parameter Table.
#define	CY_SMIF_SFDP_BFPT_BYTE_1C   (0x1CU)
	The byte 0x1C of the JEDEC Basic Flash Parameter Table.
#define	CY_SMIF_SFDP_BFPT_BYTE_1D   (0x1DU)
	The byte 0x1D of the JEDEC Basic Flash Parameter Table.
#define	CY_SMIF_SFDP_BFPT_BYTE_23   (0x23U)
	The byte 0x23 of the JEDEC Basic Flash Parameter Table.
#define	CY_SMIF_SFDP_BFPT_BYTE_28   (0x28U)
	The byte 0x28 of the JEDEC Basic Flash Parameter Table.
#define	CY_SMIF_SFDP_BFPT_BYTE_3A   (0x3AU)
	The byte 0x3A of the JEDEC Basic Flash Parameter Table.
#define	CY_SMIF_SFDP_BFPT_BYTE_3C   (0x3CU)
	The byte 0x3C of the JEDEC Basic Flash Parameter Table.
#define	CY_SMIF_SFDP_BFPT_ERASE_BYTE   (36U)
	The byte 36 of the JEDEC Basic Flash Parameter Table.
#define	CY_SMIF_JEDEC_BFPT_10TH_DWORD   (9U)
	Offset to JEDEC Basic Flash Parameter Table: 10th DWORD.
#define	CY_SMIF_JEDEC_BFPT_11TH_DWORD   (10U)
	Offset to JEDEC Basic Flash Parameter Table: 11th DWORD.
#define	CY_SMIF_SFDP_SECTOR_MAP_CMD_OFFSET   (1UL)
	The offset for the detection command instruction in the Sector Map command descriptor.
#define	CY_SMIF_SFDP_SECTOR_MAP_ADDR_CODE_OFFSET   (2UL)
	The offset for the detection command address length in the Sector Map command descriptor.
#define	CY_SMIF_SFDP_SECTOR_MAP_REG_MSK_OFFSET   (3UL)
	The offset for the read data mask in the Sector Map command descriptor.
#define	CY_SMIF_SFDP_SECTOR_MAP_REG_ADDR_OFFSET   (4UL)
	The offset for the detection command address in the Sector Map command descriptor.
#define	CY_SMIF_SFDP_SECTOR_MAP_REGION_COUNT_OFFSET   (2UL)
	The offset for the regions count in the Sector Map descriptor.
#define	CY_SMIF_SFDP_SECTOR_MAP_CONFIG_ID_OFFSET   (2UL)
	The offset for the configuration ID in the Sector Map descriptor.
#define	CY_SMIF_SFDP_SECTOR_MAP_SUPPORTED_ET_MASK   (0xFU)
	The mask for the supported erase type code in the Sector Map descriptor.
#define	CY_SMIF_SFDP_SECTOR_MAP_ADDR_BYTES_Msk   (0xC0UL)
	The mask for the configuration detection command address bytes in the Sector Map descriptor.
#define	CY_SMIF_SFDP_SECTOR_MAP_ADDR_BYTES_Pos   (6UL)
	The position of the configuration detection command address bytes in the Sector Map descriptor.
#define	CY_SMIF_SFDP_FAST_READ_1_1_4_Pos   (6UL)
	The SFDP 1-1-4 fast read support (Bit 6)
#define	CY_SMIF_SFDP_FAST_READ_1_1_4_Msk   (0x40UL)
	The SFDP 1-1-4 fast read support (Bitfield-Mask: 0x01)
#define	CY_SMIF_SFDP_FAST_READ_1_4_4_Pos   (5UL)
	The SFDP 1-4-4 fast read support (Bit 5)
#define	CY_SMIF_SFDP_FAST_READ_1_4_4_Msk   (0x20UL)
	The SFDP 1-4-4 fast read support (Bitfield-Mask: 0x01)
#define	CY_SMIF_SFDP_FAST_READ_1_2_2_Pos   (4UL)
	The SFDP 1-2-2 fast read support (Bit 4)
#define	CY_SMIF_SFDP_FAST_READ_1_2_2_Msk   (0x10UL)
	The SFDP 1-2-2 fast read support (Bitfield-Mask: 0x01)
#define	CY_SMIF_SFDP_ADDRESS_BYTES_Pos   (1UL)
	The SFDP number of address bytes (Bit 1)
#define	CY_SMIF_SFDP_ADDRESS_BYTES_Msk   (0x06UL)
	The SFDP number of address bytes (Bitfield-Mask: 0x03)
#define	CY_SMIF_SFDP_FAST_READ_1_1_2_Pos   (0UL)
	The SFDP 1-1-2 fast read support (Bit 0)
#define	CY_SMIF_SFDP_FAST_READ_1_1_2_Msk   (0x01UL)
	The SFDP 1-1-2 fast read support (Bitfield-Mask: 0x01)
#define	CY_SMIF_SFDP_SIZE_ABOVE_4GB_Msk   (0x80000000UL)
	Flash memory density bit define if it >= 4 Gbit or <= 2Gbit.
#define	CY_SMIF_SFDP_1_4_4_DUMMY_CYCLES_Pos   (0UL)
	The SFDP number of 1-4-4 fast read dummy cycles (Bit 0)
#define	CY_SMIF_SFDP_1_4_4_DUMMY_CYCLES_Msk   (0x1FUL)
	The SFDP number of 1-4-4 fast read dummy cycles (Bitfield-Mask: 0x1F)
#define	CY_SMIF_SFDP_1_4_4_MODE_CYCLES_Pos   (5UL)
	The SFDP number of 1-4-4 fast read mode cycles (Bit 5)
#define	CY_SMIF_SFDP_1_4_4_MODE_CYCLES_Msk   (0xE0UL)
	The SFDP number of 1-4-4 fast read mode cycles (Bitfield-Mask: 0x07)
#define	CY_SMIF_SFDP_1_1_4_DUMMY_CYCLES_Pos   (0UL)
	The SFDP number of 1-1-4 fast read dummy cycles (Bit 0)
#define	CY_SMIF_SFDP_1_1_4_DUMMY_CYCLES_Msk   (0x1FUL)
	The SFDP number of 1-1-4 fast read dummy cycles (Bitfield-Mask: 0x1F)
#define	CY_SMIF_SFDP_1_1_4_MODE_CYCLES_Pos   (5UL)
	The SFDP number of 1-1-4 fast read mode cycles (Bit 5)
#define	CY_SMIF_SFDP_1_1_4_MODE_CYCLES_Msk   (0xE0UL)
	The SFDP number of 1-1-4 fast read mode cycles (Bitfield-Mask: 0x07)
#define	CY_SMIF_SFDP_1_1_2_DUMMY_CYCLES_Pos   (0UL)
	The SFDP number of 1_1_2 fast read dummy cycles (Bit 0)
#define	CY_SMIF_SFDP_1_1_2_DUMMY_CYCLES_Msk   (0x1FUL)
	The SFDP number of 1_1_2 fast read dummy cycles (Bitfield-Mask: 0x1F)
#define	CY_SMIF_SFDP_1_1_2_MODE_CYCLES_Pos   (5UL)
	The SFDP number of 1_1_2 fast read mode cycles (Bit 5)
#define	CY_SMIF_SFDP_1_1_2_MODE_CYCLES_Msk   (0xE0UL)
	The SFDP number of 1_1_2 fast read mode cycles (Bitfield-Mask: 0x07)
#define	CY_SMIF_SFDP_1_2_2_DUMMY_CYCLES_Pos   (0UL)
	The SFDP number of 1_2_2 fast read dummy cycles (Bit 0)
#define	CY_SMIF_SFDP_1_2_2_DUMMY_CYCLES_Msk   (0x1FUL)
	The SFDP number of 1_2_2 fast read dummy cycles (Bitfield-Mask: 0x1F)
#define	CY_SMIF_SFDP_1_2_2_MODE_CYCLES_Pos   (5UL)
	The SFDP number of 1_2_2 fast read mode cycles (Bit 5)
#define	CY_SMIF_SFDP_1_2_2_MODE_CYCLES_Msk   (0xE0UL)
	The SFDP number of 1_2_2 fast read mode cycles (Bitfield-Mask: 0x07)
#define	CY_SMIF_SFDP_ERASE_T1_COUNT_Pos   (4UL)
	Erase Type 1 Erase, Typical time: count (Bits 8:4)
#define	CY_SMIF_SFDP_ERASE_T1_COUNT_Msk   (0x1F0UL)
	Erase Type 1 Erase, Typical time: count (Bitfield-Mask )
#define	CY_SMIF_SFDP_ERASE_T1_UNITS_Pos   (9UL)
	Erase Type 1 Erase, Typical time: units (Bits 10:9)
#define	CY_SMIF_SFDP_ERASE_T1_UNITS_Msk   (0x600UL)
	Erase Type 1 Erase, Typical time: units (Bitfield-Mask )
#define	CY_SMIF_SFDP_ERASE_MUL_COUNT_Pos   (0UL)
	Multiplier from typical erase time to maximum erase time (Bits 3:0)
#define	CY_SMIF_SFDP_ERASE_MUL_COUNT_Msk   (0x0FUL)
	Multiplier from typical erase time to maximum erase time (Bitfield-Mask )
#define	CY_SMIF_SFDP_PAGE_SIZE_Pos   (4UL)
	The SFDP page size (Bit 4)
#define	CY_SMIF_SFDP_PAGE_SIZE_Msk   (0xF0UL)
	The SFDP page size (Bitfield-Mask: 0x0F)
#define	CY_SMIF_SFDP_PAGE_PROG_COUNT_Pos   (8UL)
	The SFDP Chip Page Program Typical time: count (Bits 12:8)
#define	CY_SMIF_SFDP_PAGE_PROG_COUNT_Msk   (0x1F00UL)
	The SFDP Chip Page Program Typical time: count (Bitfield-Mask)
#define	CY_SMIF_SFDP_PAGE_PROG_UNITS_Pos   (13UL)
	The SFDP Chip Page Program Typical time: units (Bit 13)
#define	CY_SMIF_SFDP_PAGE_PROG_UNITS_Msk   (0x2000UL)
	The SFDP Chip Page Program Typical time: units (Bitfield-Mask)
#define	CY_SMIF_SFDP_CHIP_ERASE_COUNT_Pos   (24UL)
	The SFDP Chip Erase Typical time: count (Bits 28:24)
#define	CY_SMIF_SFDP_CHIP_ERASE_COUNT_Msk   (0x1F000000UL)
	The SFDP Chip Erase Typical time: count (Bitfield-Mask)
#define	CY_SMIF_SFDP_CHIP_ERASE_UNITS_Pos   (29UL)
	The SFDP Chip Erase Typical time: units (Bits 29:30)
#define	CY_SMIF_SFDP_CHIP_ERASE_UNITS_Msk   (0x60000000UL)
	The SFDP Chip Erase Typical time: units (Bitfield-Mask)
#define	CY_SMIF_SFDP_PROG_MUL_COUNT_Pos   (0UL)
	Multiplier from typical time to max time for Page or byte program (Bits 3:0)
#define	CY_SMIF_SFDP_PROG_MUL_COUNT_Msk   (0x0FUL)
	Multiplier from typical time to max time for Page or byte program (Bitfield-Mask)
#define	CY_SMIF_SFDP_QE_REQUIREMENTS_Pos   (4UL)
	The SFDP quad enable requirements field (Bit 4)
#define	CY_SMIF_SFDP_QE_REQUIREMENTS_Msk   (0x70UL)
	The SFDP quad enable requirements field (Bitfield-Mask: 0x07)
#define	CY_SMIF_SFDP_ENTER_4_BYTE_METHOD_B7   (1U)
	Issue 0xB7 instruction.
#define	CY_SMIF_SFDP_ENTER_4_BYTE_METHOD_WR_EN_B7   (2U)
	Issue write enable instruction followed with 0xB7.
#define	CY_SMIF_SFDP_ENTER_4_BYTE_METHOD_ALWAYS_4_BYTE   (0x40U)
	Memory always operates in 4-byte mode.
#define	CY_SMIF_SFDP_ENTER_4_BYTE_METHOD_B7_CMD   (0xB7U)
	The instruction required to enter 4-byte addressing mode.

Macro Definition Documentation

CY_SMIF_SFDP_SIGNATURE_BYTE_00

#define CY_SMIF_SFDP_SIGNATURE_BYTE_00   (0x00U)

The SFDP Signature byte 0x00.

Should be "S"

CY_SMIF_SFDP_SIGNATURE_BYTE_01

#define CY_SMIF_SFDP_SIGNATURE_BYTE_01   (0x01U)

The SFDP Signature byte 0x01.

Should be "F"

CY_SMIF_SFDP_SIGNATURE_BYTE_02

#define CY_SMIF_SFDP_SIGNATURE_BYTE_02   (0x02U)

The SFDP Signature byte 0x02.

Should be "D"

CY_SMIF_SFDP_SIGNATURE_BYTE_03

#define CY_SMIF_SFDP_SIGNATURE_BYTE_03   (0x03U)

The SFDP Signature byte 0x03.

Should be "P"

CY_SMIF_SFDP_MINOR_REV

#define CY_SMIF_SFDP_MINOR_REV   (0x04U)

The SFDP Header byte 0x04.

Defines the JEDEC JESD216 Revision

CY_SMIF_SFDP_MAJOR_REV

#define CY_SMIF_SFDP_MAJOR_REV   (0x05U)

The SFDP Header byte 0x05.

Defines the SFDP Major Revision

CY_SMIF_QE_BIT_STATUS_REG2_T1

#define CY_SMIF_QE_BIT_STATUS_REG2_T1   (0x02U)

The QE bit is in status register 2 type 1.

It should be written as the second byte.