TCPWM (Timer Counter PWM)

The TCPWM driver is a multifunction driver that implements Timer Counter, PWM, and Quadrature Decoder functionality using the TCPWM block. More...

Modules
	Common
	Common API for the Timer Counter PWM Block.
	Timer/Counter (TCPWM)
	Driver API for Timer/Counter.
	PWM (TCPWM)
	Driver API for PWM.
	Quadrature Decoder (TCPWM)
	Driver API for Quadrature Decoder.

Detailed Description

The TCPWM driver is a multifunction driver that implements Timer Counter, PWM, and Quadrature Decoder functionality using the TCPWM block.

The functions and other declarations used in this driver are in cy_tcpwm_counter.h, cy_tcpwm_pwm.h, cy_tcpwm_quaddec.h respectively. Include cy_pdl.h to get access to all functions and declarations in the PDL.

Each TCPWM block is a collection of counters that can all be triggered simultaneously. For each function call, the base register address of the TCPWM being used must be passed first, followed by the index of the counter you want to touch next. For some functions, you can manage multiple counters simultaneously. You provide a bit field representing each counter, rather than the single counter index).

The TCPWM supports three operating modes:

• Timer/Counter
• PWM
• Quadrature Decoder

Timer/Counter

Use this mode whenever a specific timing interval or measurement is needed. Examples include:

• Creating a periodic interrupt for running other system tasks
• Measuring frequency of an input signal
• Measuring pulse width of an input signal
• Measuring time between two external events
• Counting events
• Triggering other system resources after x number events
• Capturing time stamps when events occur

The Timer/Counter has the following features:

• Up to 8 16-bit Timers/Counters
• Programmable Period Register
• Programmable Compare Register. Compare value can be swapped with a buffered compare value on comparison event
• Capture with buffer register
• Count Up, Count Down, or Count Up and Down Counting modes
• Continuous or One Shot Run modes
• Interrupt and Output on Overflow, Underflow, Capture, or Compare
• Start, Reload, Stop, Capture, and Count Inputs

PWM

Use this mode when an output square wave is needed with a specific period and duty cycle, such as:

• Creating arbitrary square wave outputs
• Driving an LED (changing the brightness)
• Driving Motors (dead time assertion available)

The PWM has the following features:

• Up to 8 16-bit Counters
• Two Programmable Period registers that can be swapped
• Two Output Compare registers that can be swapped on overflow and/or underflow
• Left Aligned, Right Aligned, Center Aligned, and Asymmetric Aligned modes
• Continuous or One Shot run modes
• Pseudo Random mode
• Two PWM outputs with Dead Time insertion, and programmable polarity
• Interrupt and Output on Overflow, Underflow, or Compare
• Start, Reload, Stop, Swap (Capture), and Count Inputs
• Multiple Components can be synchronized together for applications such as three phase motor control

Quadrature Decoder

A quadrature decoder is used to decode the output of a quadrature encoder. A quadrature encoder senses the position, velocity, and direction of an object (for example a rotating axle, or a spinning mouse ball). A quadrature decoder can also be used for precision measurement of speed, acceleration, and position of a motor's rotor, or with a rotary switch to determine user input.
The Quadrature Decoder has the following features:

• Up to 8 16-bit Counters
• Counter Resolution of x1, x2, and x4 the frequency of the phiA (Count) and phiB (Start) inputs
• Index Input to determine absolute position
• A positive edge on phiA increments the counter when phiB is 0 and decrements the counter when phiB is 1

Configuration Considerations

For each mode, the TCPWM driver has a configuration structure, an Init function, and an Enable function.

Provide the configuration parameters in the appropriate structure (see Counter Data Structures, PWM Data Structures, or QuadDec Data Structures). Then call the appropriate Init function: Cy_TCPWM_Counter_Init, Cy_TCPWM_PWM_Init, or Cy_TCPWM_QuadDec_Init. Provide the address of the filled structure as a parameter. To enable the counter, call the appropriate Enable function: Cy_TCPWM_Counter_Enable, Cy_TCPWM_PWM_Enable, or Cy_TCPWM_QuadDec_Enable).

Many functions work with an individual counter. You can also manage multiple counters simultaneously for certain functions. These are listed in the Functions section of the TCPWM. You can enable, disable, or trigger (in various ways) multiple counters simultaneously. For these functions you provide a bit field representing each counter in the TCPWM you want to control. You can represent the bit field as an ORed mask of each counter, like ((1U << cntNumX) | (1U << cntNumX) | (1U << cntNumX)), where X is the counter number from 0 to 31.

Note

• If none of the input terminals (start, reload(index)) are used, the software event Cy_TCPWM_TriggerStart or Cy_TCPWM_TriggerReloadOrIndex must be called to start the counting.
• If count input terminal is not used, the CY_TCPWM_INPUT_LEVEL macro should be set for the countInputMode parameter and the CY_TCPWM_INPUT_1 macro should be set for the countInput parameter in the configuration structure of the appropriate mode(Counter Data Structures, PWM Data Structures, or QuadDec Data Structures).

Assign and Configure Pins

The dedicated TCPWM pins can be used. The HSIOM register must be configured to connect the block to the pins. Use the GPIO (General Purpose Input Output) driver API to do that.

Note

Initial drive state of the output pin should be aligned with expected initial state of the TCPWM output line to avoid glitches on the output line. For example, PWM output (line) with normal polarity pin should be initialized with low state.

    #if defined(CY_DEVICE_PSOC4NEXT)
        /* Scenario: P3[1] is the dedicated pin for the first counter of the TCPWM block: */
        #define HSIOM_TCPWM_LINE  P3_1_TCPWM_LINE0
    #else
        /* Scenario: P3[0] is the dedicated pin for the first counter of the TCPWM block: */
        #define HSIOM_TCPWM_LINE  P3_0_TCPWM_LINE0
    #endif
    #define GPIO_PORT         GPIO_PRT3
    

    Cy_GPIO_Pin_FastInit(GPIO_PORT, 0UL, CY_GPIO_DM_STRONG, 0UL, HSIOM_TCPWM_LINE);

Assign Clock Divider

The clock source must be connected to proper working. Any of the peripheral clock dividers could be used. Use the SysClk (System Clock) driver API to do that.

    /* Scenario: Assign the first 16-bit peripheral clock divider with
     * divide ratio = 100 to the first counter of the TCPWM block:
     */

    Cy_SysClk_PeriphAssignDivider(PCLK_TCPWM_CLOCKS0, CY_SYSCLK_DIV_16_BIT, 0UL);
    Cy_SysClk_PeriphSetDivider(CY_SYSCLK_DIV_16_BIT, 0UL, 99UL);
    Cy_SysClk_PeriphEnableDivider(CY_SYSCLK_DIV_16_BIT, 0UL);

Low Power Support

The TCPWM configuration is not recovered after Deep Sleep. User need to initialize TCPWM after deep sleep.

More Information

For more information on the TCPWM peripheral, refer to the technical reference manual (TRM).

Changelog

Version	Changes	Reason for Change
1.10.2	Update the paths to the code snippets.	PDL structure update.
	Minor documentation updates. Code snippets were updated.	Documentation enhancement.
1.10.1	Updated documentation of PWM mode.	Documentation enhancement.
1.10	Fixed Cy_TCPWM_Counter_Disable, Cy_TCPWM_PWM_Disable, and Cy_TCPWM_QuadDec_Disable functions to clear enable bit.	Fixed issue with disabling TCPWM in the Counter, PWM, and Quadrature Decoder modes.
1.0	Initial version