GPIO (General Purpose Input Output)

The GPIO driver provides an API to configure and access the device Input/Output pins. More...

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	Macros
	Functions
	Data Structures
	Enumerated Types

Detailed Description

The GPIO driver provides an API to configure and access the device Input/Output pins.

The Peripheral Driver Library(PDL) GPIO functions and other declarations used in this driver are located in cy_gpio.h. You can optionally include cy_pdl.h to get access to all the functions and declarations in the PDL.

IO pins include all general purpose types such as GPIO, HSIO, AUXIO, and their variants.

Initialization can be performed either at the port level or by configuring individual pins. Use the port configuration to efficiently use the code space. For the list of supported ports and pins, refer to the product device header files

• Single pin configuration is performed by using Cy_GPIO_Pin_FastInit (provide specific values) or Cy_GPIO_Pin_Init (provide a filled cy_stc_gpio_pin_config_t structure).
• An entire port can be configured using Cy_GPIO_Port_Init. Provide a filled cy_stc_gpio_prt_config_t structure. The values in the structure are bitfields representing the desired value for each pin in the port.
• Pin configuration and management is based on the port address and pin number. Cy_GPIO_PortToAddr function can optionally be used to calculate the port address from the port number at run-time.

Once the pin/port initialization is complete, each pin can be accessed by specifying the port (GPIO_PRT_Type) and the pin (0-7) in the provided API functions.

Configuration Considerations

1. Pin multiplexing is controlled through the High-Speed IO Matrix (HSIOM) selection. This allows the pin to connect to signal sources/sinks throughout the device, as defined by the pin HSIOM selection options (en_hsiom_sel_t). Refer to a device-specific gpio header file, e.g. <PDL_DIR>/devices/include/gpio_psoc4100sp_48_tqfp.h and the device datasheet for the supported HSIOM options.
2. All the pins are initialized to High-Z drive mode with HSIOM connected to CPU (SW control digital pin only) at Power-On-Reset(POR).
3. Some API functions perform read-modify-write operations on shared port registers. These functions are not thread safe, so the application must call them with precaution.
4. Each pin provides a digital input buffer that provides a high-impedance buffer for external digital inputs. The input buffer is connected to the HSIOM for routing to the CPU port registers and selected peripherals. Enabling the input buffer provides the possibility to read the pin state via the CPU. If a pin is connected to an analog signal, the input buffer should be disabled to avoid crowbar currents. For detail, refer to the device TRM and device datasheet.

If multiple pins on a port are updated at the same time, using direct port register writes with an appropriate port mask is more efficient than using the PDL single-pin functions. An example is shown below. Highlighted - different ways of configuring Port 1 pins using:

• Port output data register
• Port output data set register
• Port output data clear register

    GPIO_PRT_Type* portAddr;
    uint32_t value;

    /* Set the port address */
    portAddr = GPIO_PRT1;

    /* Set the drive mode to STRONG for pins P1[0], P1[2] and P1[3] (other pins in this port are HIGHZ) */
    CY_SET_REG32(&portAddr->PC, CY_GPIO_DM_STRONG << GPIO_PRT_PC_DM0_Pos |
                                CY_GPIO_DM_STRONG << GPIO_PRT_PC_DM2_Pos |
                                CY_GPIO_DM_STRONG << GPIO_PRT_PC_DM3_Pos );

    /* Set the pins P1[0], P1[2] and P1[3] to high and other pins in this port to low */
    CY_SET_REG32(&portAddr->DR, GPIO_PRT_DR_DATA0_Msk |
                                GPIO_PRT_DR_DATA2_Msk |
                                GPIO_PRT_DR_DATA3_Msk);

    /* Set the pins P1[2] and P1[3] to low (other pins in this port are unchanged) */
    CY_SET_REG32(&portAddr->DR_CLR, GPIO_PRT_DR_DATA2_Msk |
                                    GPIO_PRT_DR_DATA3_Msk);

    /* Set the pin P1[3] to high again (other pins in this port are unchanged) */
    CY_SET_REG32(&portAddr->DR_SET, GPIO_PRT_DR_DATA3_Msk);

    /* Read the port data (value should be 0b00001001) */
    value = CY_GET_REG32(&portAddr->DR);
    (void)value;

    /* Set pin P1[3] to low (other pins are not impacted) */
    CY_SET_REG32(&portAddr->DR, _CLR_SET_FLD32U(portAddr->DR, GPIO_PRT_DR_DATA3, 0u));

    /* Set pin P1[2] to high (other pins are not impacted) */
    CY_SET_REG32(&portAddr->DR, _CLR_SET_FLD32U(portAddr->DR, GPIO_PRT_DR_DATA2, 1u));

More Information

Refer to the technical reference manual (TRM) and the device datasheet.

Changelog

Version	Changes	Reason for Change
3.0	Fixed Cy_GPIO_MscControlEnable() and Cy_GPIO_MscControlDisable() implementation.	Defect fix.
	Removed reserved fields from cy_stc_gpio_prt_config_t and cy_stc_gpio_pin_config_t.	Memory usage optimization.
2.0	Fixed Cy_GPIO_Pin_Init() to configure input buffer voltage trip and output buffer slew rate properly.	Defect fix.
	Update the paths to the code snippets.	PDL structure update.
	Minor documentation updates. Code snippets were updated.	Documentation enhancement.
	Added functions for altering MSCV3LP IP block control for supported devices.	Driver enhancement.
1.20	Added Cy_GPIO_AmuxPumpEnable(), Cy_GPIO_AmuxPumpDisable, and Cy_GPIO_AmuxPumpIsEnabled() function.	The AMUXBUS charge pump support. For detail, refer to the device TRM.
1.10	Removed SIO functions. Structures cy_stc_gpio_prt_config_t and cy_stc_gpio_pin_config_t updated to drop SIO features.	No hardware support for removed features.
	Minor documentation updates.	Documentation enhancement.
1.0	Initial version