 |
MTB CAT1 Peripheral driver library
|
|
MTB CAT1 Peripheral driver library
|
Data Fields | |
| bool | enable |
| Enables/Disables TDM RX. | |
| cy_en_tdm_device_cfg_t | masterMode |
| Master mode/Slave mode configuration. More... | |
| cy_en_tdm_ws_t | wordSize |
| RX word length. More... | |
| cy_en_tdm_word_extend_cfg_t | signExtend |
| Word extension cy_en_tdm_word_extend_cfg_t. | |
| cy_en_tdm_format_t | format |
| RX data format, cy_en_tdm_format_t. More... | |
| uint16_t | clkDiv |
| Should be set to an even value ({2, 4, 6, ..., 256}), to ensure a 50/50% duty cycle clock. More... | |
| cy_en_tdm_clock_sel_t | clkSel |
| Interface clock "clk_if" selection, cy_en_tdm_clock_sel_t. More... | |
| cy_en_tdm_sckpolarity_t | sckPolarity |
| RX clock polarity, 0: as is and 1: inverted cy_en_tdm_sckpolarity_t. | |
| cy_en_tdm_fsyncpolarity_t | fsyncPolarity |
| Channel synchronization polarity:'false':used "as is". More... | |
| bool | lateSample |
| Interface late sample delay. More... | |
| cy_en_tdm_fsyncformat_t | fsyncFormat |
| Channel synchronization pulse format cy_en_tdm_fsyncformat_t. | |
| uint8_t | channelNum |
| Number of channels in the frame: 1 to 32 channels supported. More... | |
| uint8_t | channelSize |
| Channel Size. More... | |
| uint32_t | chEn |
| Channels enabled: channel i is controlled by bit chEn[i]. More... | |
| uint8_t | fifoTriggerLevel |
| Trigger level. More... | |
| uint32_t | signalInput |
| Controls routing to the RX slave signaling inputs (FSYNC/SCK): '0': RX slave signaling independent from TX signaling : '1': RX slave signaling inputs driven by TX Slave: '2': RX slave signaling inputs driven by TX Master: | |
| bool | i2sMode |
| IF set to 1 the IP is configured for I2S mode else for TDM mode. | |
| cy_en_tdm_device_cfg_t cy_stc_tdm_config_rx_t::masterMode |
Master mode/Slave mode configuration.
| cy_en_tdm_ws_t cy_stc_tdm_config_rx_t::wordSize |
RX word length.
Channel size must be greater or equal to the word size.
| cy_en_tdm_format_t cy_stc_tdm_config_rx_t::format |
RX data format, cy_en_tdm_format_t.
| uint16_t cy_stc_tdm_config_rx_t::clkDiv |
Should be set to an even value ({2, 4, 6, ..., 256}), to ensure a 50/50% duty cycle clock.
Only for Master Mode
| cy_en_tdm_clock_sel_t cy_stc_tdm_config_rx_t::clkSel |
Interface clock "clk_if" selection, cy_en_tdm_clock_sel_t.
| cy_en_tdm_fsyncpolarity_t cy_stc_tdm_config_rx_t::fsyncPolarity |
Channel synchronization polarity:'false':used "as is".
'true': inverted.
| bool cy_stc_tdm_config_rx_t::lateSample |
Interface late sample delay.
Slave configuration: "false": Sample PCM bit value on rising edge or falling edge of receiver "rx_sck_in "true": Sample PCM bit value on falling edge or rising edge of receiver "rx_sck_in" (half a cycle delay). Master configuration: "false": Sample PCM bit value on rising edge or falling edge of receiver "rx_sck_out". "true": Sample PCM bit value on falling edge or rising edge of receiver "rx_sck_out" (half a cycle delay). RISING = 0 FALLING = 1
| uint8_t cy_stc_tdm_config_rx_t::channelNum |
Number of channels in the frame: 1 to 32 channels supported.
In I2S mode number of channels should be 2.
| uint8_t cy_stc_tdm_config_rx_t::channelSize |
Channel Size.
Channel size must be greater or equal to the word size.
| uint32_t cy_stc_tdm_config_rx_t::chEn |
Channels enabled: channel i is controlled by bit chEn[i].
For example : In I2S mode for 2 channels the chEn will be 0x3
| uint8_t cy_stc_tdm_config_rx_t::fifoTriggerLevel |
Trigger level.
When the TX FIFO has less entries than the number of this field, a transmitter trigger event is generated.