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| enum | cy_en_tdm_ws_t {
CY_TDM_SIZE_8 = 0U,
CY_TDM_SIZE_10 = 1U,
CY_TDM_SIZE_12 = 2U,
CY_TDM_SIZE_14 = 3U,
CY_TDM_SIZE_16 = 4U,
CY_TDM_SIZE_18 = 5U,
CY_TDM_SIZE_20 = 6U,
CY_TDM_SIZE_24 = 7U,
CY_TDM_SIZE_32 = 8U
} |
| | cy_en_tdm_ws_t More...
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| |
| enum | cy_en_tdm_format_t {
CY_TDM_LEFT_DELAYED = 0,
CY_TDM_LEFT = 1,
CY_TDM_RIGHT_DELAYED = 2,
CY_TDM_RIGHT = 3
} |
| | cy_en_tdm_format_t More...
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| |
| enum | cy_en_tdm_device_cfg_t {
CY_TDM_DEVICE_SLAVE = 0U,
CY_TDM_DEVICE_MASTER = 1U
} |
| | cy_en_tdm_device_cfg_t More...
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| |
| enum | cy_en_tdm_word_extend_cfg_t {
CY_ZERO_EXTEND = 0U,
CY_SIGN_EXTEND = 1U
} |
| | cy_en_tdm_word_extend_cfg_t More...
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| |
| enum | cy_en_tdm_clock_sel_t {
CY_TDM_SEL_SRSS_CLK0 = 0U,
CY_TDM_SEL_SRSS_CLK1 = 1U,
CY_TDM_SEL_SRSS_CLK2 = 2U,
CY_TDM_SEL_SRSS_CLK3 = 3U,
CY_TDM_SEL_MCLK_IN = 4U
} |
| | cy_en_tdm_clock_sel_t More...
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| |
| enum | cy_en_tdm_sckpolarity_t {
CY_TDM_CLK = 0U,
CY_TDM_CLK_INVERTED = 1U
} |
| | cy_en_tdm_sckpolarity_t More...
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| |
| enum | cy_en_tdm_fsyncpolarity_t {
CY_TDM_SIGN = 0U,
CY_TDM_SIGN_INVERTED = 1U
} |
| | cy_en_tdm_fsyncpolarity_t More...
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| |
| enum | cy_en_tdm_fsyncformat_t {
CY_TDM_BIT_PERIOD = 0U,
CY_TDM_CH_PERIOD = 1U
} |
| | cy_en_tdm_fsyncformat_t More...
|
| |
| enum | cy_en_tdm_status_t {
CY_TDM_SUCCESS = 0x00UL,
CY_TDM_BAD_PARAM = CY_TDM_ID | CY_PDL_STATUS_ERROR | 0x01UL
} |
| | TDM status definitions. More...
|
| |
| enum | cy_en_tdm_source_status_t {
CY_TDM_OK = 0x00UL,
CY_TDM_BAD = 0x01UL
} |
| | cy_en_tdm_source_status_t More...
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| |
