MTB CAT1 Peripheral driver library
cy_stc_tcpwm_shiftreg_config_t Struct Reference

Description

Shift Register configuration structure.

Data Fields

uint32_t clockPrescaler
 Sets the clock prescaler inside the TCWPM block. More...
 
uint32_t tapsEnabled
 In shift register this sets the enabled taps. More...
 
uint32_t compare0
 Sets the value for Compare 0. More...
 
uint32_t compareBuf0
 Sets the value for the buffered Compare 0. More...
 
bool enableCompare0Swap
 If enabled, the compare 0 values are swapped on the terminal count. More...
 
uint32_t compare1
 Sets the value for Compare 1. More...
 
uint32_t compareBuf1
 Sets the value for the buffered Compare 1. More...
 
bool enableCompare1Swap
 If enabled, the compare1 values are swapped on the terminal count. More...
 
uint32_t interruptSources
 Enables an interrupt on the terminal count, capture or compare. More...
 
uint32_t invertShiftRegOut
 Inverts the ShiftReg output. More...
 
uint32_t invertShiftRegOutN
 Inverts the ShiftReg compliment output. More...
 
uint32_t reloadInputMode
 Configures how the reload input behaves. More...
 
uint32_t reloadInput
 Selects which input the reload uses. More...
 
uint32_t startInputMode
 Configures how the start input behaves. More...
 
uint32_t startInput
 Selects which input the start uses. More...
 
uint32_t killInputMode
 Configures how the kill0 input behaves. More...
 
uint32_t killInput
 Selects which input the kill0 uses. More...
 
uint32_t shiftInputMode
 Configures how the shift input behaves. More...
 
uint32_t shiftInput
 Selects which input the shift uses. More...
 
uint32_t serialInputMode
 Configures how the serial input behaves. More...
 
uint32_t serialInput
 Selects which input the serial uses. More...
 
uint32_t shiftRegOnDisable
 Specifies the behavior of the ShiftReg outputs line_out and line_compl_out while the Shift Register is disabled. More...
 
uint32_t trigger0Event
 Configures which internal event generates on output trigger 0. More...
 
uint32_t trigger1Event
 Configures which internal event generates on output trigger 1. More...
 
bool buffer_swap_enable
 Configures swapping mechanism between CC0 and buffered CC0, CC1 and buffered CC1, PERIOD and buffered PERIOD, DT and buffered DT.
 

Field Documentation

◆ clockPrescaler

uint32_t cy_stc_tcpwm_shiftreg_config_t::clockPrescaler

Sets the clock prescaler inside the TCWPM block.

◆ tapsEnabled

uint32_t cy_stc_tcpwm_shiftreg_config_t::tapsEnabled

In shift register this sets the enabled taps.

◆ compare0

uint32_t cy_stc_tcpwm_shiftreg_config_t::compare0

Sets the value for Compare 0.

◆ compareBuf0

uint32_t cy_stc_tcpwm_shiftreg_config_t::compareBuf0

Sets the value for the buffered Compare 0.

◆ enableCompare0Swap

bool cy_stc_tcpwm_shiftreg_config_t::enableCompare0Swap

If enabled, the compare 0 values are swapped on the terminal count.

◆ compare1

uint32_t cy_stc_tcpwm_shiftreg_config_t::compare1

Sets the value for Compare 1.

◆ compareBuf1

uint32_t cy_stc_tcpwm_shiftreg_config_t::compareBuf1

Sets the value for the buffered Compare 1.

◆ enableCompare1Swap

bool cy_stc_tcpwm_shiftreg_config_t::enableCompare1Swap

If enabled, the compare1 values are swapped on the terminal count.

◆ interruptSources

uint32_t cy_stc_tcpwm_shiftreg_config_t::interruptSources

Enables an interrupt on the terminal count, capture or compare.

◆ invertShiftRegOut

uint32_t cy_stc_tcpwm_shiftreg_config_t::invertShiftRegOut

Inverts the ShiftReg output.

◆ invertShiftRegOutN

uint32_t cy_stc_tcpwm_shiftreg_config_t::invertShiftRegOutN

Inverts the ShiftReg compliment output.

◆ reloadInputMode

uint32_t cy_stc_tcpwm_shiftreg_config_t::reloadInputMode

Configures how the reload input behaves.

◆ reloadInput

uint32_t cy_stc_tcpwm_shiftreg_config_t::reloadInput

Selects which input the reload uses.

The inputs are device-specific.

◆ startInputMode

uint32_t cy_stc_tcpwm_shiftreg_config_t::startInputMode

Configures how the start input behaves.

See Input Modes.

◆ startInput

uint32_t cy_stc_tcpwm_shiftreg_config_t::startInput

Selects which input the start uses.

The inputs are device-specific.

◆ killInputMode

uint32_t cy_stc_tcpwm_shiftreg_config_t::killInputMode

Configures how the kill0 input behaves.

◆ killInput

uint32_t cy_stc_tcpwm_shiftreg_config_t::killInput

Selects which input the kill0 uses.

The inputs are device-specific.

◆ shiftInputMode

uint32_t cy_stc_tcpwm_shiftreg_config_t::shiftInputMode

Configures how the shift input behaves.

◆ shiftInput

uint32_t cy_stc_tcpwm_shiftreg_config_t::shiftInput

Selects which input the shift uses.

The inputs are device-specific.

◆ serialInputMode

uint32_t cy_stc_tcpwm_shiftreg_config_t::serialInputMode

Configures how the serial input behaves.

◆ serialInput

uint32_t cy_stc_tcpwm_shiftreg_config_t::serialInput

Selects which input the serial uses.

Inputs are device-specific.

◆ shiftRegOnDisable

uint32_t cy_stc_tcpwm_shiftreg_config_t::shiftRegOnDisable

Specifies the behavior of the ShiftReg outputs line_out and line_compl_out while the Shift Register is disabled.

◆ trigger0Event

uint32_t cy_stc_tcpwm_shiftreg_config_t::trigger0Event

Configures which internal event generates on output trigger 0.

◆ trigger1Event

uint32_t cy_stc_tcpwm_shiftreg_config_t::trigger1Event

Configures which internal event generates on output trigger 1.