MTB CAT1 Peripheral driver library
cy_stc_pdm_pcm_config_t Struct Reference

Description

PDM-PCM initialization configuration.

Data Fields

cy_en_pdm_pcm_clk_div_t clkDiv
 PDM Clock Divider (1st divider), see cy_en_pdm_pcm_clk_div_t This configures a frequency of PDM CLK. More...
 
cy_en_pdm_pcm_clk_div_t mclkDiv
 MCLKQ divider (2nd divider), see cy_en_pdm_pcm_clk_div_t.
 
uint8_t ckoDiv
 PDM CKO (FPDM_CKO) clock divider (3rd divider): More...
 
uint8_t ckoDelay
 Extra PDM_CKO delay to internal sampler: More...
 
uint8_t sincDecRate
 F(MCLK_L_R) = Fs * 2 * sincDecRate * mclkDiv, Fs is a sampling frequency, 8 kHz - 48 kHz.
 
cy_en_pdm_pcm_out_t chanSelect
 see cy_en_pdm_pcm_out_t
 
bool chanSwapEnable
 Audio channels swapping.
 
uint8_t highPassFilterGain
 High pass filter gain: H(Z) = (1 - Z^-1) / (1 - (1 - 2^highPassFilterGain) * Z^-1)
 
bool highPassDisable
 High pass filter disable.
 
cy_en_pdm_pcm_s_cycles_t softMuteCycles
 The time step for gain change during PGA or soft mute operation in number of 1/a sampling rate, see cy_en_pdm_pcm_s_cycles_t. More...
 
uint32_t softMuteFineGain
 Soft mute fine gain: 0 = 0.13dB, 1 = 0.26dB.
 
bool softMuteEnable
 Soft mute enable.
 
cy_en_pdm_pcm_word_len_t wordLen
 see cy_en_pdm_pcm_word_len_t
 
bool signExtension
 Word extension type: More...
 
cy_en_pdm_pcm_gain_t gainLeft
 Gain for left channel, see cy_en_pdm_pcm_gain_t.
 
cy_en_pdm_pcm_gain_t gainRight
 Gain for right channel, see cy_en_pdm_pcm_gain_t.
 
uint8_t rxFifoTriggerLevel
 Fifo interrupt trigger level (in words), range: 0 - 253 for stereo and 0 - 254 for mono mode.
 
bool dmaTriggerEnable
 DMA trigger enable.
 
uint32_t interruptMask
 Interrupts enable mask.
 

Field Documentation

◆ clkDiv

cy_en_pdm_pcm_clk_div_t cy_stc_pdm_pcm_config_t::clkDiv

PDM Clock Divider (1st divider), see cy_en_pdm_pcm_clk_div_t This configures a frequency of PDM CLK.

The configured frequency is used to operate PDM core. I.e. the frequency is input to MCLKQ_CLOCK_DIV register.

◆ ckoDiv

uint8_t cy_stc_pdm_pcm_config_t::ckoDiv

PDM CKO (FPDM_CKO) clock divider (3rd divider):

  • if CKO_CLOCK_DIV >= 1 - *F(PDM_CKO) = F(PDM_CLK / (mclkDiv + 1))
  • if CKO_CLOCK_DIV = 0 - *F(PDM_CKO) = MCLKQ / 2

◆ ckoDelay

uint8_t cy_stc_pdm_pcm_config_t::ckoDelay

Extra PDM_CKO delay to internal sampler:

  • 0: Three extra PDM_CLK period advance
  • 1: Two extra PDM_CLK period advance
  • 2: One extra PDM_CLK period advance
  • 3: No delay
  • 4: One extra PDM_CLK period delay
  • 5: Two extra PDM_CLK period delay
  • 6: Three extra PDM_CLK period delay
  • 7: Four extra PDM_CLK clock delay

◆ softMuteCycles

cy_en_pdm_pcm_s_cycles_t cy_stc_pdm_pcm_config_t::softMuteCycles

The time step for gain change during PGA or soft mute operation in number of 1/a sampling rate, see cy_en_pdm_pcm_s_cycles_t.

◆ signExtension

bool cy_stc_pdm_pcm_config_t::signExtension

Word extension type:

  • 0: extension by zero
  • 1: extension by sign bits