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| enum | cy_en_pdm_pcm_word_len_t {
CY_PDM_PCM_WLEN_16_BIT = 0U,
CY_PDM_PCM_WLEN_18_BIT = 1U,
CY_PDM_PCM_WLEN_20_BIT = 2U,
CY_PDM_PCM_WLEN_24_BIT = 3U
} |
| | PDM Word Length. More...
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| |
| enum | cy_en_pdm_pcm_clk_div_t {
CY_PDM_PCM_CLK_DIV_BYPASS = 0U,
CY_PDM_PCM_CLK_DIV_1_2 = 1U,
CY_PDM_PCM_CLK_DIV_1_3 = 2U,
CY_PDM_PCM_CLK_DIV_1_4 = 3U
} |
| | PDM Clock Divider. More...
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| |
| enum | cy_en_pdm_pcm_out_t {
CY_PDM_PCM_OUT_CHAN_LEFT = 1U,
CY_PDM_PCM_OUT_CHAN_RIGHT = 2U,
CY_PDM_PCM_OUT_STEREO = 3U
} |
| | PDM Output Mode. More...
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| |
| enum | cy_en_pdm_pcm_chan_select_t {
CY_PDM_PCM_CHAN_LEFT = 0U,
CY_PDM_PCM_CHAN_RIGHT = 1U
} |
| | PDM Channel selector. More...
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| |
| enum | cy_en_pdm_pcm_gain_t {
CY_PDM_PCM_ATTN_12_DB = 0U,
CY_PDM_PCM_ATTN_10_5_DB = 1U,
CY_PDM_PCM_ATTN_9_DB = 2U,
CY_PDM_PCM_ATTN_7_5_DB = 3U,
CY_PDM_PCM_ATTN_6_DB = 4U,
CY_PDM_PCM_ATTN_4_5_DB = 5U,
CY_PDM_PCM_ATTN_3_DB = 6U,
CY_PDM_PCM_ATTN_1_5_DB = 7U,
CY_PDM_PCM_BYPASS = 8U,
CY_PDM_PCM_GAIN_1_5_DB = 9U,
CY_PDM_PCM_GAIN_3_DB = 10U,
CY_PDM_PCM_GAIN_4_5_DB = 11U,
CY_PDM_PCM_GAIN_6_DB = 12U,
CY_PDM_PCM_GAIN_7_5_DB = 13U,
CY_PDM_PCM_GAIN_9_DB = 14U,
CY_PDM_PCM_GAIN_10_5_DB = 15U
} |
| | PDM Gain. More...
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| enum | cy_en_pdm_pcm_s_cycles_t {
CY_PDM_PCM_SOFT_MUTE_CYCLES_64 = 0U,
CY_PDM_PCM_SOFT_MUTE_CYCLES_96 = 1U,
CY_PDM_PCM_SOFT_MUTE_CYCLES_128 = 2U,
CY_PDM_PCM_SOFT_MUTE_CYCLES_160 = 3U,
CY_PDM_PCM_SOFT_MUTE_CYCLES_192 = 4U,
CY_PDM_PCM_SOFT_MUTE_CYCLES_256 = 5U,
CY_PDM_PCM_SOFT_MUTE_CYCLES_384 = 6U,
CY_PDM_PCM_SOFT_MUTE_CYCLES_512 = 7U
} |
| | The time step for gain change during PGA or soft mute operation in number of 1/a sampling rate. More...
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| enum | cy_en_pdm_pcm_status_t {
CY_PDM_PCM_SUCCESS = 0x00UL,
CY_PDM_PCM_BAD_PARAM = CY_PDM_PCM_ID | CY_PDL_STATUS_ERROR | 0x01UL,
CY_PDM_PCM_SUCCESS = 0x00UL,
CY_PDM_PCM_BAD_PARAM = CY_PDM_PCM_V2_ID | CY_PDL_STATUS_ERROR |0x01UL
} |
| | The PDM-PCM status codes. More...
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