Macros | |
#define | CY_SYS_CM4_STATUS_ENABLED (3U) |
The Cortex-M4 core is enabled: power on, clock on, no isolate, no reset and no retain. More... | |
#define | CY_SYS_CM4_STATUS_DISABLED (0U) |
The Cortex-M4 core is disabled: power off, clock off, isolate, reset and no retain. More... | |
#define | CY_SYS_CM4_STATUS_RETAINED (2U) |
The Cortex-M4 core is retained. More... | |
#define | CY_SYS_CM4_STATUS_RESET (1U) |
The Cortex-M4 core is in the Reset mode: clock off, no isolated, no retain and reset. More... | |
#define CY_SYS_CM4_STATUS_ENABLED (3U) |
The Cortex-M4 core is enabled: power on, clock on, no isolate, no reset and no retain.
#define CY_SYS_CM4_STATUS_DISABLED (0U) |
The Cortex-M4 core is disabled: power off, clock off, isolate, reset and no retain.
#define CY_SYS_CM4_STATUS_RETAINED (2U) |
The Cortex-M4 core is retained.
power off, clock off, isolate, no reset and retain.
#define CY_SYS_CM4_STATUS_RESET (1U) |
The Cortex-M4 core is in the Reset mode: clock off, no isolated, no retain and reset.