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MTB CAT1 Peripheral driver library
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MTB CAT1 Peripheral driver library
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Define RESET_CAUSE mask values.
Macros | |
| #define | CY_SYSLIB_RESET_HWWDT (0x0001U) |
| A basic WatchDog Timer (WDT) reset has occurred since the last power cycle. More... | |
| #define | CY_SYSLIB_RESET_ACT_FAULT (0x0002U) |
| The fault logging system requested a reset from its Active logic. More... | |
| #define | CY_SYSLIB_RESET_DPSLP_FAULT (0x0004U) |
| The fault logging system requested a reset from its Deep-Sleep logic. More... | |
| #define | CY_SYSLIB_RESET_TC_DBGRESET (0x0008U) |
| The fault logging system requested a reset from its Test Controller or debugger asserted test. More... | |
| #define | CY_SYSLIB_RESET_SOFT (0x0010U) |
| The CPU requested a system reset through it's SYSRESETREQ. More... | |
| #define | CY_SYSLIB_RESET_SWWDT0 (0x0020U) |
| The Multi-Counter Watchdog timer #0 reset has occurred since the last power cycle. More... | |
| #define | CY_SYSLIB_RESET_SWWDT1 (0x0040U) |
| The Multi-Counter Watchdog timer #1 reset has occurred since the last power cycle. More... | |
| #define | CY_SYSLIB_RESET_SWWDT2 (0x0080U) |
| The Multi-Counter Watchdog timer #2 reset has occurred since the last power cycle. More... | |
| #define | CY_SYSLIB_RESET_SWWDT3 (0x0100U) |
| The Multi-Counter Watchdog timer #3 reset has occurred since the last power cycle. More... | |
| #define | CY_SYSLIB_RESET_CSV_LOSS_WAKEUP (0x10000U) |
| The reset has occurred on a loss of high-frequency clock. More... | |
| #define | CY_SYSLIB_RESET_CSV_ERROR_WAKEUP (0x20000U) |
| The reset has occurred due to frequency error of high-frequency clock. More... | |
| #define | CY_SYSLIB_RESET_HIB_WAKEUP (0x80000000U) |
| The reset has occurred on a wakeup from Hibernate power mode. More... | |
| #define | CY_SYSLIB_RESET_XRES (0x10000U) |
| External XRES pin was asserted. More... | |
| #define | CY_SYSLIB_RESET_BODVDDD (0x20000U) |
| External VDDD supply crossed brown-out limit. More... | |
| #define | CY_SYSLIB_RESET_BODVDDA (0x40000U) |
| External VDDA supply crossed the brown-out limit. More... | |
| #define | CY_SYSLIB_RESET_BODVCCD (0x80000U) |
| Internal VCCD core supply crossed the brown-out limit. More... | |
| #define | CY_SYSLIB_RESET_OVDVDDD (0x100000U) |
| Overvoltage detection on the external VDDD supply. More... | |
| #define | CY_SYSLIB_RESET_OVDVDDA (0x200000U) |
| Overvoltage detection on the external VDDA supply. More... | |
| #define | CY_SYSLIB_RESET_OVDVCCD (0x400000U) |
| Overvoltage detection on the internal core VCCD supply. More... | |
| #define | CY_SYSLIB_RESET_OCD_ACT_LINREG (0x800000U) |
| Overcurrent detection on the internal VCCD supply when supplied by the ACTIVE power mode linear regulator. More... | |
| #define | CY_SYSLIB_RESET_OCD_DPSLP_LINREG (0x1000000U) |
| Overcurrent detection on the internal VCCD supply when supplied by the DEEPSLEEP power mode linear regulator. More... | |
| #define | CY_SYSLIB_RESET_OCD_REGHC (0x2000000U) |
| Overcurrent detection from REGHC (if present). More... | |
| #define | CY_SYSLIB_RESET_PMIC (0x4000000U) |
| PMIC status triggered a reset. More... | |
| #define | CY_SYSLIB_RESET_PXRES (0x10000000U) |
| PXRES triggered. More... | |
| #define | CY_SYSLIB_RESET_STRUCT_XRES (0x20000000U) |
| Structural reset was asserted. More... | |
| #define | CY_SYSLIB_RESET_PORVDDD (0x40000000U) |
| Indicator that a POR occurred. More... | |
| #define CY_SYSLIB_RESET_HWWDT (0x0001U) |
A basic WatchDog Timer (WDT) reset has occurred since the last power cycle.
| #define CY_SYSLIB_RESET_ACT_FAULT (0x0002U) |
The fault logging system requested a reset from its Active logic.
| #define CY_SYSLIB_RESET_DPSLP_FAULT (0x0004U) |
The fault logging system requested a reset from its Deep-Sleep logic.
| #define CY_SYSLIB_RESET_TC_DBGRESET (0x0008U) |
The fault logging system requested a reset from its Test Controller or debugger asserted test.
| #define CY_SYSLIB_RESET_SOFT (0x0010U) |
The CPU requested a system reset through it's SYSRESETREQ.
This can be done via a debugger probe or in firmware.
| #define CY_SYSLIB_RESET_SWWDT0 (0x0020U) |
The Multi-Counter Watchdog timer #0 reset has occurred since the last power cycle.
| #define CY_SYSLIB_RESET_SWWDT1 (0x0040U) |
The Multi-Counter Watchdog timer #1 reset has occurred since the last power cycle.
| #define CY_SYSLIB_RESET_SWWDT2 (0x0080U) |
The Multi-Counter Watchdog timer #2 reset has occurred since the last power cycle.
| #define CY_SYSLIB_RESET_SWWDT3 (0x0100U) |
The Multi-Counter Watchdog timer #3 reset has occurred since the last power cycle.
| #define CY_SYSLIB_RESET_CSV_LOSS_WAKEUP (0x10000U) |
The reset has occurred on a loss of high-frequency clock.
| #define CY_SYSLIB_RESET_CSV_ERROR_WAKEUP (0x20000U) |
The reset has occurred due to frequency error of high-frequency clock.
| #define CY_SYSLIB_RESET_HIB_WAKEUP (0x80000000U) |
The reset has occurred on a wakeup from Hibernate power mode.
| #define CY_SYSLIB_RESET_XRES (0x10000U) |
External XRES pin was asserted.
| #define CY_SYSLIB_RESET_BODVDDD (0x20000U) |
External VDDD supply crossed brown-out limit.
Note that this cause will only be observable as long as the VDDD supply does not go below the POR (power on reset) detection limit.
| #define CY_SYSLIB_RESET_BODVDDA (0x40000U) |
External VDDA supply crossed the brown-out limit.
This is a high-voltage cause bit that blocks recording of other high-voltage cause bits, except RESET_PORVDDD.
| #define CY_SYSLIB_RESET_BODVCCD (0x80000U) |
Internal VCCD core supply crossed the brown-out limit.
Note that this detector will detect gross issues with the internal core supply, but may not catch all brown-out conditions.
| #define CY_SYSLIB_RESET_OVDVDDD (0x100000U) |
Overvoltage detection on the external VDDD supply.
This is a high-voltage cause bit that blocks recording of other high-voltage cause bits, except RESET_PORVDDD.
| #define CY_SYSLIB_RESET_OVDVDDA (0x200000U) |
Overvoltage detection on the external VDDA supply.
This is a high-voltage cause bit that blocks recording of other high-voltage cause bits, except RESET_PORVDDD.
| #define CY_SYSLIB_RESET_OVDVCCD (0x400000U) |
Overvoltage detection on the internal core VCCD supply.
This is a high-voltage cause bit that blocks recording of other high-voltage cause bits, except RESET_PORVDDD.
| #define CY_SYSLIB_RESET_OCD_ACT_LINREG (0x800000U) |
Overcurrent detection on the internal VCCD supply when supplied by the ACTIVE power mode linear regulator.
This is a high-voltage cause bit that blocks recording of other high-voltage cause bits, except RESET_PORVDDD.
| #define CY_SYSLIB_RESET_OCD_DPSLP_LINREG (0x1000000U) |
Overcurrent detection on the internal VCCD supply when supplied by the DEEPSLEEP power mode linear regulator.
This is a high-voltage cause bit that blocks recording of other high-voltage cause bits, except RESET_PORVDDD.
| #define CY_SYSLIB_RESET_OCD_REGHC (0x2000000U) |
Overcurrent detection from REGHC (if present).
If REGHC is not present, hardware will never set this bit.This is a high-voltage cause bit that blocks recording of other high-voltage cause bits, except RESET_PORVDDD.
| #define CY_SYSLIB_RESET_PMIC (0x4000000U) |
PMIC status triggered a reset.
If PMIC control is not present, hardware will never set this bit. This is a high-voltage cause bit that blocks recording of other high-voltage cause bits, except RESET_PORVDDD.
| #define CY_SYSLIB_RESET_PXRES (0x10000000U) |
PXRES triggered.
This is a high-voltage cause bit that blocks recording of other high-voltage cause bits, except RESET_PORVDDD. Hardware clears this bit during POR.
| #define CY_SYSLIB_RESET_STRUCT_XRES (0x20000000U) |
Structural reset was asserted.
This is a high-voltage cause bit that blocks recording of other high-voltage cause bits, except RESET_PORVDDD. Hardware clears this bit during POR.
| #define CY_SYSLIB_RESET_PORVDDD (0x40000000U) |
Indicator that a POR occurred.
This is a high-voltage cause bit, and hardware clears the other bits when this one is set. It does not block further recording of other high-voltage causes.