MTB CAT1 Peripheral driver library

General Description

Enumerations

enum  cy_en_pll_400M_ssgc_depth_t {
  CY_SYSCLK_SSCG_DEPTH_MINUS_0_5 = 0x029u,
  CY_SYSCLK_SSCG_DEPTH_MINUS_1_0 = 0x052u,
  CY_SYSCLK_SSCG_DEPTH_MINUS_2_0 = 0x0A4u,
  CY_SYSCLK_SSCG_DEPTH_MINUS_3_0 = 0x0F6u
}
 SSCG modulation depth of PLL 400M spreading mode. More...
 
enum  cy_en_pll_400M_ssgc_rate_t {
  CY_SYSCLK_SSCG_RATE_DIV_4096 = 0u,
  CY_SYSCLK_SSCG_RATE_DIV_2048 = 1u,
  CY_SYSCLK_SSCG_RATE_DIV_1024 = 2u,
  CY_SYSCLK_SSCG_RATE_DIV_512 = 3u,
  CY_SYSCLK_SSCG_RATE_DIV_256 = 4u
}
 SSCG modulation rate of PLL 400M spreading mode. More...
 

Enumeration Type Documentation

◆ cy_en_pll_400M_ssgc_depth_t

SSCG modulation depth of PLL 400M spreading mode.

See registers SSCG_DEPTH bit of PLL400M_STRUCT_CONFIG3.

Enumerator
CY_SYSCLK_SSCG_DEPTH_MINUS_0_5 
  • 0.5 [%] (down spread)
CY_SYSCLK_SSCG_DEPTH_MINUS_1_0 
  • 1.0 [%] (down spread)
CY_SYSCLK_SSCG_DEPTH_MINUS_2_0 
  • 2.0 [%] (down spread)
CY_SYSCLK_SSCG_DEPTH_MINUS_3_0 
  • 3.0 [%] (down spread)

◆ cy_en_pll_400M_ssgc_rate_t

SSCG modulation rate of PLL 400M spreading mode.

See registers SSCG_RATE bit of PLL400M_STRUCT_CONFIG3.

Enumerator
CY_SYSCLK_SSCG_RATE_DIV_4096 

Modulation rate = fPFD/4096.

CY_SYSCLK_SSCG_RATE_DIV_2048 

Modulation rate = fPFD/2048.

CY_SYSCLK_SSCG_RATE_DIV_1024 

Modulation rate = fPFD/1024.

CY_SYSCLK_SSCG_RATE_DIV_512 

Modulation rate = fPFD/512.

CY_SYSCLK_SSCG_RATE_DIV_256 

Modulation rate = fPFD/256.