Macros | |
#define | CY_HPPASS_SAR_GRP_NUM (8U) |
The number of Sequencer Groups. | |
#define | CY_HPPASS_SAR_CHAN_NUM (28U) |
The number of channels. | |
#define | CY_HPPASS_SAR_SAMP_TIME_NUM (3U) |
The number of sample timers. | |
#define | CY_HPPASS_SAR_LIMIT_NUM (8U) |
The number of limit crossing detection blocks. | |
#define | CY_HPPASS_SAR_DIR_SAMP_NUM (12U) |
The number of the direct samplers. | |
#define | CY_HPPASS_SAR_MUX_SAMP_NUM (4U) |
The number of the muxed samplers. | |
#define | CY_HPPASS_FIR_NUM (2U) |
The number of FIR filters. | |
#define | CY_HPPASS_FIR_TAP_NUM (16U) |
The number of FIR filter taps. | |
#define | CY_HPPASS_FIFO_NUM (4U) |
The number of the FIFO pieces. | |
#define | CY_HPPASS_SAR_SAMPLERS_DISABLED (0x0U) |
All the samplers are disabled. More... | |
#define | CY_HPPASS_SAR_CHAN_RSLT_PTR(chanIdx) ((volatile const uint32_t *)&HPPASS_SAR_CHAN_RESULT(HPPASS_BASE, (chanIdx))) |
The pointer to the Channel Result register, useful for e.g. More... | |
#define | CY_HPPASS_SAR_FIR_RSLT_PTR(firIdx) ((volatile const uint32_t *)&HPPASS_SAR_FIR_RESULT(HPPASS_BASE, (firIdx))) |
The pointer to the FIR Result register, useful for e.g. More... | |
#define | CY_HPPASS_SAR_FIFO_READ_PTR(fifoIdx) ((volatile const uint32_t *)&HPPASS_MMIO_FIFO_RD_DATA(HPPASS_BASE, (fifoIdx))) |
The pointer to the FIFO Read Data register, useful for e.g. More... | |
#define CY_HPPASS_SAR_SAMPLERS_DISABLED (0x0U) |
All the samplers are disabled.
#define CY_HPPASS_SAR_CHAN_RSLT_PTR | ( | chanIdx | ) | ((volatile const uint32_t *)&HPPASS_SAR_CHAN_RESULT(HPPASS_BASE, (chanIdx))) |
The pointer to the Channel Result register, useful for e.g.
DMA descriptor initialization
#define CY_HPPASS_SAR_FIR_RSLT_PTR | ( | firIdx | ) | ((volatile const uint32_t *)&HPPASS_SAR_FIR_RESULT(HPPASS_BASE, (firIdx))) |
The pointer to the FIR Result register, useful for e.g.
DMA descriptor initialization
#define CY_HPPASS_SAR_FIFO_READ_PTR | ( | fifoIdx | ) | ((volatile const uint32_t *)&HPPASS_MMIO_FIFO_RD_DATA(HPPASS_BASE, (fifoIdx))) |
The pointer to the FIFO Read Data register, useful for e.g.
DMA descriptor initialization