PSOC4100SMAX

General Description

Trigger connections for psoc4100smax.

Macros
#define	CYHAL_TRIGGER_CPUSS_ZERO   (CYHAL_TRIGGER_CPUSS_ZERO_LEVEL)
	Deprecated defines for signals that can be either level or edge. More...
#define	CYHAL_TRIGGER_CPUSS_DMAC_TR_OUT0   (CYHAL_TRIGGER_CPUSS_DMAC_TR_OUT0_LEVEL)
	Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
#define	CYHAL_TRIGGER_CPUSS_DMAC_TR_OUT1   (CYHAL_TRIGGER_CPUSS_DMAC_TR_OUT1_LEVEL)
	Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
#define	CYHAL_TRIGGER_CPUSS_DMAC_TR_OUT2   (CYHAL_TRIGGER_CPUSS_DMAC_TR_OUT2_LEVEL)
	Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
#define	CYHAL_TRIGGER_CPUSS_DMAC_TR_OUT3   (CYHAL_TRIGGER_CPUSS_DMAC_TR_OUT3_LEVEL)
	Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
#define	CYHAL_TRIGGER_CPUSS_DMAC_TR_OUT4   (CYHAL_TRIGGER_CPUSS_DMAC_TR_OUT4_LEVEL)
	Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
#define	CYHAL_TRIGGER_CPUSS_DMAC_TR_OUT5   (CYHAL_TRIGGER_CPUSS_DMAC_TR_OUT5_LEVEL)
	Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
#define	CYHAL_TRIGGER_CPUSS_DMAC_TR_OUT6   (CYHAL_TRIGGER_CPUSS_DMAC_TR_OUT6_LEVEL)
	Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
#define	CYHAL_TRIGGER_CPUSS_DMAC_TR_OUT7   (CYHAL_TRIGGER_CPUSS_DMAC_TR_OUT7_LEVEL)
	Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
#define	CYHAL_TRIGGER_CPUSS_DMAC_TR_OUT8   (CYHAL_TRIGGER_CPUSS_DMAC_TR_OUT8_LEVEL)
	Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
#define	CYHAL_TRIGGER_CPUSS_DMAC_TR_OUT9   (CYHAL_TRIGGER_CPUSS_DMAC_TR_OUT9_LEVEL)
	Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
#define	CYHAL_TRIGGER_CPUSS_DMAC_TR_OUT10   (CYHAL_TRIGGER_CPUSS_DMAC_TR_OUT10_LEVEL)
	Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
#define	CYHAL_TRIGGER_CPUSS_DMAC_TR_OUT11   (CYHAL_TRIGGER_CPUSS_DMAC_TR_OUT11_LEVEL)
	Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
#define	CYHAL_TRIGGER_CPUSS_DMAC_TR_OUT12   (CYHAL_TRIGGER_CPUSS_DMAC_TR_OUT12_LEVEL)
	Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
#define	CYHAL_TRIGGER_CPUSS_DMAC_TR_OUT13   (CYHAL_TRIGGER_CPUSS_DMAC_TR_OUT13_LEVEL)
	Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
#define	CYHAL_TRIGGER_CPUSS_DMAC_TR_OUT14   (CYHAL_TRIGGER_CPUSS_DMAC_TR_OUT14_LEVEL)
	Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
#define	CYHAL_TRIGGER_CPUSS_DMAC_TR_OUT15   (CYHAL_TRIGGER_CPUSS_DMAC_TR_OUT15_LEVEL)
	Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
#define	CYHAL_TRIGGER_EXCO_TRIGGER   (CYHAL_TRIGGER_EXCO_TRIGGER_LEVEL)
	Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
#define	CYHAL_TRIGGER_LPCOMP_COMP_OUT0   (CYHAL_TRIGGER_LPCOMP_COMP_OUT0_LEVEL)
	Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
#define	CYHAL_TRIGGER_LPCOMP_COMP_OUT1   (CYHAL_TRIGGER_LPCOMP_COMP_OUT1_LEVEL)
	Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
#define	CYHAL_TRIGGER_PASS0_DSI_CTB_CMP0   (CYHAL_TRIGGER_PASS0_DSI_CTB_CMP0_LEVEL)
	Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
#define	CYHAL_TRIGGER_PASS0_DSI_CTB_CMP1   (CYHAL_TRIGGER_PASS0_DSI_CTB_CMP1_LEVEL)
	Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
#define	CYHAL_TRIGGER_PASS0_DSI_SAR_SAMPLE_DONE   (CYHAL_TRIGGER_PASS0_DSI_SAR_SAMPLE_DONE_LEVEL)
	Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
#define	CYHAL_TRIGGER_PASS0_TR_SAR_OUT   (CYHAL_TRIGGER_PASS0_TR_SAR_OUT_LEVEL)
	Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
#define	CYHAL_TRIGGER_TCPWM_LINE0   (CYHAL_TRIGGER_TCPWM_LINE0_LEVEL)
	Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
#define	CYHAL_TRIGGER_TCPWM_LINE1   (CYHAL_TRIGGER_TCPWM_LINE1_LEVEL)
	Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
#define	CYHAL_TRIGGER_TCPWM_LINE2   (CYHAL_TRIGGER_TCPWM_LINE2_LEVEL)
	Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
#define	CYHAL_TRIGGER_TCPWM_LINE3   (CYHAL_TRIGGER_TCPWM_LINE3_LEVEL)
	Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
#define	CYHAL_TRIGGER_TCPWM_LINE4   (CYHAL_TRIGGER_TCPWM_LINE4_LEVEL)
	Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
#define	CYHAL_TRIGGER_TCPWM_LINE5   (CYHAL_TRIGGER_TCPWM_LINE5_LEVEL)
	Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
#define	CYHAL_TRIGGER_TCPWM_LINE6   (CYHAL_TRIGGER_TCPWM_LINE6_LEVEL)
	Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
#define	CYHAL_TRIGGER_TCPWM_LINE7   (CYHAL_TRIGGER_TCPWM_LINE7_LEVEL)
	Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
#define	CYHAL_TRIGGER_TCPWM_TR_COMPARE_MATCH0   (CYHAL_TRIGGER_TCPWM_TR_COMPARE_MATCH0_LEVEL)
	Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
#define	CYHAL_TRIGGER_TCPWM_TR_COMPARE_MATCH1   (CYHAL_TRIGGER_TCPWM_TR_COMPARE_MATCH1_LEVEL)
	Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
#define	CYHAL_TRIGGER_TCPWM_TR_COMPARE_MATCH2   (CYHAL_TRIGGER_TCPWM_TR_COMPARE_MATCH2_LEVEL)
	Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
#define	CYHAL_TRIGGER_TCPWM_TR_COMPARE_MATCH3   (CYHAL_TRIGGER_TCPWM_TR_COMPARE_MATCH3_LEVEL)
	Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
#define	CYHAL_TRIGGER_TCPWM_TR_COMPARE_MATCH4   (CYHAL_TRIGGER_TCPWM_TR_COMPARE_MATCH4_LEVEL)
	Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
#define	CYHAL_TRIGGER_TCPWM_TR_COMPARE_MATCH5   (CYHAL_TRIGGER_TCPWM_TR_COMPARE_MATCH5_LEVEL)
	Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
#define	CYHAL_TRIGGER_TCPWM_TR_COMPARE_MATCH6   (CYHAL_TRIGGER_TCPWM_TR_COMPARE_MATCH6_LEVEL)
	Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
#define	CYHAL_TRIGGER_TCPWM_TR_COMPARE_MATCH7   (CYHAL_TRIGGER_TCPWM_TR_COMPARE_MATCH7_LEVEL)
	Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
#define	CYHAL_TRIGGER_TCPWM_TR_OVERFLOW0   (CYHAL_TRIGGER_TCPWM_TR_OVERFLOW0_LEVEL)
	Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
#define	CYHAL_TRIGGER_TCPWM_TR_OVERFLOW1   (CYHAL_TRIGGER_TCPWM_TR_OVERFLOW1_LEVEL)
	Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
#define	CYHAL_TRIGGER_TCPWM_TR_OVERFLOW2   (CYHAL_TRIGGER_TCPWM_TR_OVERFLOW2_LEVEL)
	Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
#define	CYHAL_TRIGGER_TCPWM_TR_OVERFLOW3   (CYHAL_TRIGGER_TCPWM_TR_OVERFLOW3_LEVEL)
	Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
#define	CYHAL_TRIGGER_TCPWM_TR_OVERFLOW4   (CYHAL_TRIGGER_TCPWM_TR_OVERFLOW4_LEVEL)
	Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
#define	CYHAL_TRIGGER_TCPWM_TR_OVERFLOW5   (CYHAL_TRIGGER_TCPWM_TR_OVERFLOW5_LEVEL)
	Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
#define	CYHAL_TRIGGER_TCPWM_TR_OVERFLOW6   (CYHAL_TRIGGER_TCPWM_TR_OVERFLOW6_LEVEL)
	Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
#define	CYHAL_TRIGGER_TCPWM_TR_OVERFLOW7   (CYHAL_TRIGGER_TCPWM_TR_OVERFLOW7_LEVEL)
	Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
#define	CYHAL_TRIGGER_TCPWM_TR_UNDERFLOW0   (CYHAL_TRIGGER_TCPWM_TR_UNDERFLOW0_LEVEL)
	Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
#define	CYHAL_TRIGGER_TCPWM_TR_UNDERFLOW1   (CYHAL_TRIGGER_TCPWM_TR_UNDERFLOW1_LEVEL)
	Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
#define	CYHAL_TRIGGER_TCPWM_TR_UNDERFLOW2   (CYHAL_TRIGGER_TCPWM_TR_UNDERFLOW2_LEVEL)
	Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
#define	CYHAL_TRIGGER_TCPWM_TR_UNDERFLOW3   (CYHAL_TRIGGER_TCPWM_TR_UNDERFLOW3_LEVEL)
	Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
#define	CYHAL_TRIGGER_TCPWM_TR_UNDERFLOW4   (CYHAL_TRIGGER_TCPWM_TR_UNDERFLOW4_LEVEL)
	Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
#define	CYHAL_TRIGGER_TCPWM_TR_UNDERFLOW5   (CYHAL_TRIGGER_TCPWM_TR_UNDERFLOW5_LEVEL)
	Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
#define	CYHAL_TRIGGER_TCPWM_TR_UNDERFLOW6   (CYHAL_TRIGGER_TCPWM_TR_UNDERFLOW6_LEVEL)
	Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
#define	CYHAL_TRIGGER_TCPWM_TR_UNDERFLOW7   (CYHAL_TRIGGER_TCPWM_TR_UNDERFLOW7_LEVEL)
	Legacy define. Instead, use the explicit _LEVEL or _EDGE version.

Typedefs
typedef cyhal_trigger_source_psoc4100smax_t	cyhal_source_t
	Typedef from device family specific trigger source to generic trigger source.
typedef cyhal_trigger_dest_psoc4100smax_t	cyhal_dest_t
	Typedef from device family specific trigger dest to generic trigger dest.

Enumerations
enum	cyhal_trigger_source_psoc4100smax_t {   CYHAL_TRIGGER_CPUSS_ZERO_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_ZERO, CYHAL_SIGNAL_TYPE_EDGE),   CYHAL_TRIGGER_CPUSS_ZERO_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_ZERO, CYHAL_SIGNAL_TYPE_LEVEL),   CYHAL_TRIGGER_CANFD_TR_DBG_DMA_REQ0 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CANFD_TR_DBG_DMA_REQ0, CYHAL_SIGNAL_TYPE_LEVEL),   CYHAL_TRIGGER_CANFD_TR_FIFO00 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CANFD_TR_FIFO00, CYHAL_SIGNAL_TYPE_LEVEL),   CYHAL_TRIGGER_CANFD_TR_FIFO10 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CANFD_TR_FIFO10, CYHAL_SIGNAL_TYPE_LEVEL),   CYHAL_TRIGGER_CANFD_TR_TMP_RTP_OUT0 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CANFD_TR_TMP_RTP_OUT0, CYHAL_SIGNAL_TYPE_EDGE),   CYHAL_TRIGGER_CPUSS_DMAC_TR_OUT0_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DMAC_TR_OUT0, CYHAL_SIGNAL_TYPE_EDGE),   CYHAL_TRIGGER_CPUSS_DMAC_TR_OUT0_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DMAC_TR_OUT0, CYHAL_SIGNAL_TYPE_LEVEL),   CYHAL_TRIGGER_CPUSS_DMAC_TR_OUT1_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DMAC_TR_OUT1, CYHAL_SIGNAL_TYPE_EDGE),   CYHAL_TRIGGER_CPUSS_DMAC_TR_OUT1_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DMAC_TR_OUT1, CYHAL_SIGNAL_TYPE_LEVEL),   CYHAL_TRIGGER_CPUSS_DMAC_TR_OUT2_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DMAC_TR_OUT2, CYHAL_SIGNAL_TYPE_EDGE),   CYHAL_TRIGGER_CPUSS_DMAC_TR_OUT2_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DMAC_TR_OUT2, CYHAL_SIGNAL_TYPE_LEVEL),   CYHAL_TRIGGER_CPUSS_DMAC_TR_OUT3_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DMAC_TR_OUT3, CYHAL_SIGNAL_TYPE_EDGE),   CYHAL_TRIGGER_CPUSS_DMAC_TR_OUT3_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DMAC_TR_OUT3, CYHAL_SIGNAL_TYPE_LEVEL),   CYHAL_TRIGGER_CPUSS_DMAC_TR_OUT4_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DMAC_TR_OUT4, CYHAL_SIGNAL_TYPE_EDGE),   CYHAL_TRIGGER_CPUSS_DMAC_TR_OUT4_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DMAC_TR_OUT4, CYHAL_SIGNAL_TYPE_LEVEL),   CYHAL_TRIGGER_CPUSS_DMAC_TR_OUT5_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DMAC_TR_OUT5, CYHAL_SIGNAL_TYPE_EDGE),   CYHAL_TRIGGER_CPUSS_DMAC_TR_OUT5_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DMAC_TR_OUT5, CYHAL_SIGNAL_TYPE_LEVEL),   CYHAL_TRIGGER_CPUSS_DMAC_TR_OUT6_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DMAC_TR_OUT6, CYHAL_SIGNAL_TYPE_EDGE),   CYHAL_TRIGGER_CPUSS_DMAC_TR_OUT6_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DMAC_TR_OUT6, CYHAL_SIGNAL_TYPE_LEVEL),   CYHAL_TRIGGER_CPUSS_DMAC_TR_OUT7_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DMAC_TR_OUT7, CYHAL_SIGNAL_TYPE_EDGE),   CYHAL_TRIGGER_CPUSS_DMAC_TR_OUT7_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DMAC_TR_OUT7, CYHAL_SIGNAL_TYPE_LEVEL),   CYHAL_TRIGGER_CPUSS_DMAC_TR_OUT8_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DMAC_TR_OUT8, CYHAL_SIGNAL_TYPE_EDGE),   CYHAL_TRIGGER_CPUSS_DMAC_TR_OUT8_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DMAC_TR_OUT8, CYHAL_SIGNAL_TYPE_LEVEL),   CYHAL_TRIGGER_CPUSS_DMAC_TR_OUT9_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DMAC_TR_OUT9, CYHAL_SIGNAL_TYPE_EDGE),   CYHAL_TRIGGER_CPUSS_DMAC_TR_OUT9_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DMAC_TR_OUT9, CYHAL_SIGNAL_TYPE_LEVEL),   CYHAL_TRIGGER_CPUSS_DMAC_TR_OUT10_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DMAC_TR_OUT10, CYHAL_SIGNAL_TYPE_EDGE),   CYHAL_TRIGGER_CPUSS_DMAC_TR_OUT10_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DMAC_TR_OUT10, CYHAL_SIGNAL_TYPE_LEVEL),   CYHAL_TRIGGER_CPUSS_DMAC_TR_OUT11_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DMAC_TR_OUT11, CYHAL_SIGNAL_TYPE_EDGE),   CYHAL_TRIGGER_CPUSS_DMAC_TR_OUT11_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DMAC_TR_OUT11, CYHAL_SIGNAL_TYPE_LEVEL),   CYHAL_TRIGGER_CPUSS_DMAC_TR_OUT12_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DMAC_TR_OUT12, CYHAL_SIGNAL_TYPE_EDGE),   CYHAL_TRIGGER_CPUSS_DMAC_TR_OUT12_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DMAC_TR_OUT12, CYHAL_SIGNAL_TYPE_LEVEL),   CYHAL_TRIGGER_CPUSS_DMAC_TR_OUT13_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DMAC_TR_OUT13, CYHAL_SIGNAL_TYPE_EDGE),   CYHAL_TRIGGER_CPUSS_DMAC_TR_OUT13_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DMAC_TR_OUT13, CYHAL_SIGNAL_TYPE_LEVEL),   CYHAL_TRIGGER_CPUSS_DMAC_TR_OUT14_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DMAC_TR_OUT14, CYHAL_SIGNAL_TYPE_EDGE),   CYHAL_TRIGGER_CPUSS_DMAC_TR_OUT14_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DMAC_TR_OUT14, CYHAL_SIGNAL_TYPE_LEVEL),   CYHAL_TRIGGER_CPUSS_DMAC_TR_OUT15_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DMAC_TR_OUT15, CYHAL_SIGNAL_TYPE_EDGE),   CYHAL_TRIGGER_CPUSS_DMAC_TR_OUT15_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DMAC_TR_OUT15, CYHAL_SIGNAL_TYPE_LEVEL),   CYHAL_TRIGGER_EXCO_TRIGGER_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_EXCO_TRIGGER, CYHAL_SIGNAL_TYPE_EDGE),   CYHAL_TRIGGER_EXCO_TRIGGER_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_EXCO_TRIGGER, CYHAL_SIGNAL_TYPE_LEVEL),   CYHAL_TRIGGER_LPCOMP_COMP_OUT0_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_LPCOMP_COMP_OUT0, CYHAL_SIGNAL_TYPE_EDGE),   CYHAL_TRIGGER_LPCOMP_COMP_OUT0_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_LPCOMP_COMP_OUT0, CYHAL_SIGNAL_TYPE_LEVEL),   CYHAL_TRIGGER_LPCOMP_COMP_OUT1_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_LPCOMP_COMP_OUT1, CYHAL_SIGNAL_TYPE_EDGE),   CYHAL_TRIGGER_LPCOMP_COMP_OUT1_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_LPCOMP_COMP_OUT1, CYHAL_SIGNAL_TYPE_LEVEL),   CYHAL_TRIGGER_MSC0_TR_RD_REQ_OUT = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_MSC0_TR_RD_REQ_OUT, CYHAL_SIGNAL_TYPE_EDGE),   CYHAL_TRIGGER_MSC1_TR_RD_REQ_OUT = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_MSC1_TR_RD_REQ_OUT, CYHAL_SIGNAL_TYPE_EDGE),   CYHAL_TRIGGER_MSC0_TR_WR_REQ_OUT = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_MSC0_TR_WR_REQ_OUT, CYHAL_SIGNAL_TYPE_EDGE),   CYHAL_TRIGGER_MSC1_TR_WR_REQ_OUT = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_MSC1_TR_WR_REQ_OUT, CYHAL_SIGNAL_TYPE_EDGE),   CYHAL_TRIGGER_PASS0_DSI_CTB_CMP0_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_DSI_CTB_CMP0, CYHAL_SIGNAL_TYPE_EDGE),   CYHAL_TRIGGER_PASS0_DSI_CTB_CMP0_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_DSI_CTB_CMP0, CYHAL_SIGNAL_TYPE_LEVEL),   CYHAL_TRIGGER_PASS0_DSI_CTB_CMP1_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_DSI_CTB_CMP1, CYHAL_SIGNAL_TYPE_EDGE),   CYHAL_TRIGGER_PASS0_DSI_CTB_CMP1_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_DSI_CTB_CMP1, CYHAL_SIGNAL_TYPE_LEVEL),   CYHAL_TRIGGER_PASS0_DSI_SAR_SAMPLE_DONE_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_DSI_SAR_SAMPLE_DONE, CYHAL_SIGNAL_TYPE_EDGE),   CYHAL_TRIGGER_PASS0_DSI_SAR_SAMPLE_DONE_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_DSI_SAR_SAMPLE_DONE, CYHAL_SIGNAL_TYPE_LEVEL),   CYHAL_TRIGGER_PASS0_TR_SAR_OUT_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_OUT, CYHAL_SIGNAL_TYPE_EDGE),   CYHAL_TRIGGER_PASS0_TR_SAR_OUT_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_OUT, CYHAL_SIGNAL_TYPE_LEVEL),   CYHAL_TRIGGER_SCB0_TR_I2C_SCL_FILTERED = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_SCB0_TR_I2C_SCL_FILTERED, CYHAL_SIGNAL_TYPE_LEVEL),   CYHAL_TRIGGER_SCB1_TR_I2C_SCL_FILTERED = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_SCB1_TR_I2C_SCL_FILTERED, CYHAL_SIGNAL_TYPE_LEVEL),   CYHAL_TRIGGER_SCB2_TR_I2C_SCL_FILTERED = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_SCB2_TR_I2C_SCL_FILTERED, CYHAL_SIGNAL_TYPE_LEVEL),   CYHAL_TRIGGER_SCB3_TR_I2C_SCL_FILTERED = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_SCB3_TR_I2C_SCL_FILTERED, CYHAL_SIGNAL_TYPE_LEVEL),   CYHAL_TRIGGER_SCB4_TR_I2C_SCL_FILTERED = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_SCB4_TR_I2C_SCL_FILTERED, CYHAL_SIGNAL_TYPE_LEVEL),   CYHAL_TRIGGER_SCB0_TR_RX_REQ = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_SCB0_TR_RX_REQ, CYHAL_SIGNAL_TYPE_LEVEL),   CYHAL_TRIGGER_SCB1_TR_RX_REQ = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_SCB1_TR_RX_REQ, CYHAL_SIGNAL_TYPE_LEVEL),   CYHAL_TRIGGER_SCB2_TR_RX_REQ = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_SCB2_TR_RX_REQ, CYHAL_SIGNAL_TYPE_LEVEL),   CYHAL_TRIGGER_SCB3_TR_RX_REQ = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_SCB3_TR_RX_REQ, CYHAL_SIGNAL_TYPE_LEVEL),   CYHAL_TRIGGER_SCB4_TR_RX_REQ = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_SCB4_TR_RX_REQ, CYHAL_SIGNAL_TYPE_LEVEL),   CYHAL_TRIGGER_SCB0_TR_TX_REQ = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_SCB0_TR_TX_REQ, CYHAL_SIGNAL_TYPE_LEVEL),   CYHAL_TRIGGER_SCB1_TR_TX_REQ = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_SCB1_TR_TX_REQ, CYHAL_SIGNAL_TYPE_LEVEL),   CYHAL_TRIGGER_SCB2_TR_TX_REQ = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_SCB2_TR_TX_REQ, CYHAL_SIGNAL_TYPE_LEVEL),   CYHAL_TRIGGER_SCB3_TR_TX_REQ = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_SCB3_TR_TX_REQ, CYHAL_SIGNAL_TYPE_LEVEL),   CYHAL_TRIGGER_SCB4_TR_TX_REQ = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_SCB4_TR_TX_REQ, CYHAL_SIGNAL_TYPE_LEVEL),   CYHAL_TRIGGER_TCPWM_LINE0_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM_LINE0, CYHAL_SIGNAL_TYPE_EDGE),   CYHAL_TRIGGER_TCPWM_LINE0_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM_LINE0, CYHAL_SIGNAL_TYPE_LEVEL),   CYHAL_TRIGGER_TCPWM_LINE1_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM_LINE1, CYHAL_SIGNAL_TYPE_EDGE),   CYHAL_TRIGGER_TCPWM_LINE1_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM_LINE1, CYHAL_SIGNAL_TYPE_LEVEL),   CYHAL_TRIGGER_TCPWM_LINE2_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM_LINE2, CYHAL_SIGNAL_TYPE_EDGE),   CYHAL_TRIGGER_TCPWM_LINE2_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM_LINE2, CYHAL_SIGNAL_TYPE_LEVEL),   CYHAL_TRIGGER_TCPWM_LINE3_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM_LINE3, CYHAL_SIGNAL_TYPE_EDGE),   CYHAL_TRIGGER_TCPWM_LINE3_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM_LINE3, CYHAL_SIGNAL_TYPE_LEVEL),   CYHAL_TRIGGER_TCPWM_LINE4_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM_LINE4, CYHAL_SIGNAL_TYPE_EDGE),   CYHAL_TRIGGER_TCPWM_LINE4_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM_LINE4, CYHAL_SIGNAL_TYPE_LEVEL),   CYHAL_TRIGGER_TCPWM_LINE5_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM_LINE5, CYHAL_SIGNAL_TYPE_EDGE),   CYHAL_TRIGGER_TCPWM_LINE5_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM_LINE5, CYHAL_SIGNAL_TYPE_LEVEL),   CYHAL_TRIGGER_TCPWM_LINE6_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM_LINE6, CYHAL_SIGNAL_TYPE_EDGE),   CYHAL_TRIGGER_TCPWM_LINE6_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM_LINE6, CYHAL_SIGNAL_TYPE_LEVEL),   CYHAL_TRIGGER_TCPWM_LINE7_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM_LINE7, CYHAL_SIGNAL_TYPE_EDGE),   CYHAL_TRIGGER_TCPWM_LINE7_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM_LINE7, CYHAL_SIGNAL_TYPE_LEVEL),   CYHAL_TRIGGER_TCPWM_TR_COMPARE_MATCH0_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM_TR_COMPARE_MATCH0, CYHAL_SIGNAL_TYPE_EDGE),   CYHAL_TRIGGER_TCPWM_TR_COMPARE_MATCH0_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM_TR_COMPARE_MATCH0, CYHAL_SIGNAL_TYPE_LEVEL),   CYHAL_TRIGGER_TCPWM_TR_COMPARE_MATCH1_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM_TR_COMPARE_MATCH1, CYHAL_SIGNAL_TYPE_EDGE),   CYHAL_TRIGGER_TCPWM_TR_COMPARE_MATCH1_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM_TR_COMPARE_MATCH1, CYHAL_SIGNAL_TYPE_LEVEL),   CYHAL_TRIGGER_TCPWM_TR_COMPARE_MATCH2_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM_TR_COMPARE_MATCH2, CYHAL_SIGNAL_TYPE_EDGE),   CYHAL_TRIGGER_TCPWM_TR_COMPARE_MATCH2_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM_TR_COMPARE_MATCH2, CYHAL_SIGNAL_TYPE_LEVEL),   CYHAL_TRIGGER_TCPWM_TR_COMPARE_MATCH3_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM_TR_COMPARE_MATCH3, CYHAL_SIGNAL_TYPE_EDGE),   CYHAL_TRIGGER_TCPWM_TR_COMPARE_MATCH3_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM_TR_COMPARE_MATCH3, CYHAL_SIGNAL_TYPE_LEVEL),   CYHAL_TRIGGER_TCPWM_TR_COMPARE_MATCH4_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM_TR_COMPARE_MATCH4, CYHAL_SIGNAL_TYPE_EDGE),   CYHAL_TRIGGER_TCPWM_TR_COMPARE_MATCH4_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM_TR_COMPARE_MATCH4, CYHAL_SIGNAL_TYPE_LEVEL),   CYHAL_TRIGGER_TCPWM_TR_COMPARE_MATCH5_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM_TR_COMPARE_MATCH5, CYHAL_SIGNAL_TYPE_EDGE),   CYHAL_TRIGGER_TCPWM_TR_COMPARE_MATCH5_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM_TR_COMPARE_MATCH5, CYHAL_SIGNAL_TYPE_LEVEL),   CYHAL_TRIGGER_TCPWM_TR_COMPARE_MATCH6_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM_TR_COMPARE_MATCH6, CYHAL_SIGNAL_TYPE_EDGE),   CYHAL_TRIGGER_TCPWM_TR_COMPARE_MATCH6_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM_TR_COMPARE_MATCH6, CYHAL_SIGNAL_TYPE_LEVEL),   CYHAL_TRIGGER_TCPWM_TR_COMPARE_MATCH7_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM_TR_COMPARE_MATCH7, CYHAL_SIGNAL_TYPE_EDGE),   CYHAL_TRIGGER_TCPWM_TR_COMPARE_MATCH7_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM_TR_COMPARE_MATCH7, CYHAL_SIGNAL_TYPE_LEVEL),   CYHAL_TRIGGER_TCPWM_TR_OVERFLOW0_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM_TR_OVERFLOW0, CYHAL_SIGNAL_TYPE_EDGE),   CYHAL_TRIGGER_TCPWM_TR_OVERFLOW0_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM_TR_OVERFLOW0, CYHAL_SIGNAL_TYPE_LEVEL),   CYHAL_TRIGGER_TCPWM_TR_OVERFLOW1_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM_TR_OVERFLOW1, CYHAL_SIGNAL_TYPE_EDGE),   CYHAL_TRIGGER_TCPWM_TR_OVERFLOW1_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM_TR_OVERFLOW1, CYHAL_SIGNAL_TYPE_LEVEL),   CYHAL_TRIGGER_TCPWM_TR_OVERFLOW2_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM_TR_OVERFLOW2, CYHAL_SIGNAL_TYPE_EDGE),   CYHAL_TRIGGER_TCPWM_TR_OVERFLOW2_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM_TR_OVERFLOW2, CYHAL_SIGNAL_TYPE_LEVEL),   CYHAL_TRIGGER_TCPWM_TR_OVERFLOW3_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM_TR_OVERFLOW3, CYHAL_SIGNAL_TYPE_EDGE),   CYHAL_TRIGGER_TCPWM_TR_OVERFLOW3_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM_TR_OVERFLOW3, CYHAL_SIGNAL_TYPE_LEVEL),   CYHAL_TRIGGER_TCPWM_TR_OVERFLOW4_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM_TR_OVERFLOW4, CYHAL_SIGNAL_TYPE_EDGE),   CYHAL_TRIGGER_TCPWM_TR_OVERFLOW4_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM_TR_OVERFLOW4, CYHAL_SIGNAL_TYPE_LEVEL),   CYHAL_TRIGGER_TCPWM_TR_OVERFLOW5_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM_TR_OVERFLOW5, CYHAL_SIGNAL_TYPE_EDGE),   CYHAL_TRIGGER_TCPWM_TR_OVERFLOW5_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM_TR_OVERFLOW5, CYHAL_SIGNAL_TYPE_LEVEL),   CYHAL_TRIGGER_TCPWM_TR_OVERFLOW6_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM_TR_OVERFLOW6, CYHAL_SIGNAL_TYPE_EDGE),   CYHAL_TRIGGER_TCPWM_TR_OVERFLOW6_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM_TR_OVERFLOW6, CYHAL_SIGNAL_TYPE_LEVEL),   CYHAL_TRIGGER_TCPWM_TR_OVERFLOW7_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM_TR_OVERFLOW7, CYHAL_SIGNAL_TYPE_EDGE),   CYHAL_TRIGGER_TCPWM_TR_OVERFLOW7_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM_TR_OVERFLOW7, CYHAL_SIGNAL_TYPE_LEVEL),   CYHAL_TRIGGER_TCPWM_TR_UNDERFLOW0_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM_TR_UNDERFLOW0, CYHAL_SIGNAL_TYPE_EDGE),   CYHAL_TRIGGER_TCPWM_TR_UNDERFLOW0_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM_TR_UNDERFLOW0, CYHAL_SIGNAL_TYPE_LEVEL),   CYHAL_TRIGGER_TCPWM_TR_UNDERFLOW1_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM_TR_UNDERFLOW1, CYHAL_SIGNAL_TYPE_EDGE),   CYHAL_TRIGGER_TCPWM_TR_UNDERFLOW1_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM_TR_UNDERFLOW1, CYHAL_SIGNAL_TYPE_LEVEL),   CYHAL_TRIGGER_TCPWM_TR_UNDERFLOW2_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM_TR_UNDERFLOW2, CYHAL_SIGNAL_TYPE_EDGE),   CYHAL_TRIGGER_TCPWM_TR_UNDERFLOW2_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM_TR_UNDERFLOW2, CYHAL_SIGNAL_TYPE_LEVEL),   CYHAL_TRIGGER_TCPWM_TR_UNDERFLOW3_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM_TR_UNDERFLOW3, CYHAL_SIGNAL_TYPE_EDGE),   CYHAL_TRIGGER_TCPWM_TR_UNDERFLOW3_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM_TR_UNDERFLOW3, CYHAL_SIGNAL_TYPE_LEVEL),   CYHAL_TRIGGER_TCPWM_TR_UNDERFLOW4_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM_TR_UNDERFLOW4, CYHAL_SIGNAL_TYPE_EDGE),   CYHAL_TRIGGER_TCPWM_TR_UNDERFLOW4_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM_TR_UNDERFLOW4, CYHAL_SIGNAL_TYPE_LEVEL),   CYHAL_TRIGGER_TCPWM_TR_UNDERFLOW5_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM_TR_UNDERFLOW5, CYHAL_SIGNAL_TYPE_EDGE),   CYHAL_TRIGGER_TCPWM_TR_UNDERFLOW5_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM_TR_UNDERFLOW5, CYHAL_SIGNAL_TYPE_LEVEL),   CYHAL_TRIGGER_TCPWM_TR_UNDERFLOW6_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM_TR_UNDERFLOW6, CYHAL_SIGNAL_TYPE_EDGE),   CYHAL_TRIGGER_TCPWM_TR_UNDERFLOW6_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM_TR_UNDERFLOW6, CYHAL_SIGNAL_TYPE_LEVEL),   CYHAL_TRIGGER_TCPWM_TR_UNDERFLOW7_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM_TR_UNDERFLOW7, CYHAL_SIGNAL_TYPE_EDGE),   CYHAL_TRIGGER_TCPWM_TR_UNDERFLOW7_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM_TR_UNDERFLOW7, CYHAL_SIGNAL_TYPE_LEVEL) }
	Name of each input trigger. More...
enum	cyhal_trigger_dest_psoc4100smax_t {   CYHAL_TRIGGER_CANFD_TR_DBG_DMA_ACK0 = 0,   CYHAL_TRIGGER_CANFD_TR_EVT_SWT_IN0 = 1,   CYHAL_TRIGGER_CPUSS_DMAC_TR_IN0 = 2,   CYHAL_TRIGGER_CPUSS_DMAC_TR_IN1 = 3,   CYHAL_TRIGGER_CPUSS_DMAC_TR_IN2 = 4,   CYHAL_TRIGGER_CPUSS_DMAC_TR_IN3 = 5,   CYHAL_TRIGGER_CPUSS_DMAC_TR_IN4 = 6,   CYHAL_TRIGGER_CPUSS_DMAC_TR_IN5 = 7,   CYHAL_TRIGGER_CPUSS_DMAC_TR_IN6 = 8,   CYHAL_TRIGGER_CPUSS_DMAC_TR_IN7 = 9,   CYHAL_TRIGGER_CPUSS_DMAC_TR_IN8 = 10,   CYHAL_TRIGGER_CPUSS_DMAC_TR_IN9 = 11,   CYHAL_TRIGGER_CPUSS_DMAC_TR_IN10 = 12,   CYHAL_TRIGGER_CPUSS_DMAC_TR_IN11 = 13,   CYHAL_TRIGGER_CPUSS_DMAC_TR_IN12 = 14,   CYHAL_TRIGGER_CPUSS_DMAC_TR_IN13 = 15,   CYHAL_TRIGGER_CPUSS_DMAC_TR_IN14 = 16,   CYHAL_TRIGGER_CPUSS_DMAC_TR_IN15 = 17,   CYHAL_TRIGGER_MSC0_TR_RD_REQ_IN = 18,   CYHAL_TRIGGER_MSC1_TR_RD_REQ_IN = 19,   CYHAL_TRIGGER_MSC0_TR_WR_REQ_IN = 20,   CYHAL_TRIGGER_MSC1_TR_WR_REQ_IN = 21,   CYHAL_TRIGGER_PASS0_TR_SAR_IN = 22,   CYHAL_TRIGGER_TCPWM_TR_IN7 = 23,   CYHAL_TRIGGER_TCPWM_TR_IN8 = 24,   CYHAL_TRIGGER_TCPWM_TR_IN9 = 25,   CYHAL_TRIGGER_TCPWM_TR_IN10 = 26,   CYHAL_TRIGGER_TCPWM_TR_IN11 = 27,   CYHAL_TRIGGER_TCPWM_TR_IN12 = 28,   CYHAL_TRIGGER_TCPWM_TR_IN13 = 29 }
	Name of each output trigger. More...

Macro Definition Documentation

CYHAL_TRIGGER_CPUSS_ZERO

#define CYHAL_TRIGGER_CPUSS_ZERO   (CYHAL_TRIGGER_CPUSS_ZERO_LEVEL)

Deprecated defines for signals that can be either level or edge.

Legacy define. Instead, use the explicit _LEVEL or _EDGE version.

Enumeration Type Documentation

cyhal_trigger_source_psoc4100smax_t

enum cyhal_trigger_source_psoc4100smax_t

Name of each input trigger.

Enumerator
CYHAL_TRIGGER_CPUSS_ZERO_EDGE	cpuss.zero
CYHAL_TRIGGER_CPUSS_ZERO_LEVEL	cpuss.zero
CYHAL_TRIGGER_CANFD_TR_DBG_DMA_REQ0	canfd.tr_dbg_dma_req[0]
CYHAL_TRIGGER_CANFD_TR_FIFO00	canfd.tr_fifo0[0]
CYHAL_TRIGGER_CANFD_TR_FIFO10	canfd.tr_fifo1[0]
CYHAL_TRIGGER_CANFD_TR_TMP_RTP_OUT0	canfd.tr_tmp_rtp_out[0]
CYHAL_TRIGGER_CPUSS_DMAC_TR_OUT0_EDGE	cpuss.dmac_tr_out[0]
CYHAL_TRIGGER_CPUSS_DMAC_TR_OUT0_LEVEL	cpuss.dmac_tr_out[0]
CYHAL_TRIGGER_CPUSS_DMAC_TR_OUT1_EDGE	cpuss.dmac_tr_out[1]
CYHAL_TRIGGER_CPUSS_DMAC_TR_OUT1_LEVEL	cpuss.dmac_tr_out[1]
CYHAL_TRIGGER_CPUSS_DMAC_TR_OUT2_EDGE	cpuss.dmac_tr_out[2]
CYHAL_TRIGGER_CPUSS_DMAC_TR_OUT2_LEVEL	cpuss.dmac_tr_out[2]
CYHAL_TRIGGER_CPUSS_DMAC_TR_OUT3_EDGE	cpuss.dmac_tr_out[3]
CYHAL_TRIGGER_CPUSS_DMAC_TR_OUT3_LEVEL	cpuss.dmac_tr_out[3]
CYHAL_TRIGGER_CPUSS_DMAC_TR_OUT4_EDGE	cpuss.dmac_tr_out[4]
CYHAL_TRIGGER_CPUSS_DMAC_TR_OUT4_LEVEL	cpuss.dmac_tr_out[4]
CYHAL_TRIGGER_CPUSS_DMAC_TR_OUT5_EDGE	cpuss.dmac_tr_out[5]
CYHAL_TRIGGER_CPUSS_DMAC_TR_OUT5_LEVEL	cpuss.dmac_tr_out[5]
CYHAL_TRIGGER_CPUSS_DMAC_TR_OUT6_EDGE	cpuss.dmac_tr_out[6]
CYHAL_TRIGGER_CPUSS_DMAC_TR_OUT6_LEVEL	cpuss.dmac_tr_out[6]
CYHAL_TRIGGER_CPUSS_DMAC_TR_OUT7_EDGE	cpuss.dmac_tr_out[7]
CYHAL_TRIGGER_CPUSS_DMAC_TR_OUT7_LEVEL	cpuss.dmac_tr_out[7]
CYHAL_TRIGGER_CPUSS_DMAC_TR_OUT8_EDGE	cpuss.dmac_tr_out[8]
CYHAL_TRIGGER_CPUSS_DMAC_TR_OUT8_LEVEL	cpuss.dmac_tr_out[8]
CYHAL_TRIGGER_CPUSS_DMAC_TR_OUT9_EDGE	cpuss.dmac_tr_out[9]
CYHAL_TRIGGER_CPUSS_DMAC_TR_OUT9_LEVEL	cpuss.dmac_tr_out[9]
CYHAL_TRIGGER_CPUSS_DMAC_TR_OUT10_EDGE	cpuss.dmac_tr_out[10]
CYHAL_TRIGGER_CPUSS_DMAC_TR_OUT10_LEVEL	cpuss.dmac_tr_out[10]
CYHAL_TRIGGER_CPUSS_DMAC_TR_OUT11_EDGE	cpuss.dmac_tr_out[11]
CYHAL_TRIGGER_CPUSS_DMAC_TR_OUT11_LEVEL	cpuss.dmac_tr_out[11]
CYHAL_TRIGGER_CPUSS_DMAC_TR_OUT12_EDGE	cpuss.dmac_tr_out[12]
CYHAL_TRIGGER_CPUSS_DMAC_TR_OUT12_LEVEL	cpuss.dmac_tr_out[12]
CYHAL_TRIGGER_CPUSS_DMAC_TR_OUT13_EDGE	cpuss.dmac_tr_out[13]
CYHAL_TRIGGER_CPUSS_DMAC_TR_OUT13_LEVEL	cpuss.dmac_tr_out[13]
CYHAL_TRIGGER_CPUSS_DMAC_TR_OUT14_EDGE	cpuss.dmac_tr_out[14]
CYHAL_TRIGGER_CPUSS_DMAC_TR_OUT14_LEVEL	cpuss.dmac_tr_out[14]
CYHAL_TRIGGER_CPUSS_DMAC_TR_OUT15_EDGE	cpuss.dmac_tr_out[15]
CYHAL_TRIGGER_CPUSS_DMAC_TR_OUT15_LEVEL	cpuss.dmac_tr_out[15]
CYHAL_TRIGGER_EXCO_TRIGGER_EDGE	exco.trigger
CYHAL_TRIGGER_EXCO_TRIGGER_LEVEL	exco.trigger
CYHAL_TRIGGER_LPCOMP_COMP_OUT0_EDGE	lpcomp.comp_out[0]
CYHAL_TRIGGER_LPCOMP_COMP_OUT0_LEVEL	lpcomp.comp_out[0]
CYHAL_TRIGGER_LPCOMP_COMP_OUT1_EDGE	lpcomp.comp_out[1]
CYHAL_TRIGGER_LPCOMP_COMP_OUT1_LEVEL	lpcomp.comp_out[1]
CYHAL_TRIGGER_MSC0_TR_RD_REQ_OUT	msc[0].tr_rd_req_out
CYHAL_TRIGGER_MSC1_TR_RD_REQ_OUT	msc[1].tr_rd_req_out
CYHAL_TRIGGER_MSC0_TR_WR_REQ_OUT	msc[0].tr_wr_req_out
CYHAL_TRIGGER_MSC1_TR_WR_REQ_OUT	msc[1].tr_wr_req_out
CYHAL_TRIGGER_PASS0_DSI_CTB_CMP0_EDGE	pass[0].dsi_ctb_cmp0
CYHAL_TRIGGER_PASS0_DSI_CTB_CMP0_LEVEL	pass[0].dsi_ctb_cmp0
CYHAL_TRIGGER_PASS0_DSI_CTB_CMP1_EDGE	pass[0].dsi_ctb_cmp1
CYHAL_TRIGGER_PASS0_DSI_CTB_CMP1_LEVEL	pass[0].dsi_ctb_cmp1
CYHAL_TRIGGER_PASS0_DSI_SAR_SAMPLE_DONE_EDGE	pass[0].dsi_sar_sample_done
CYHAL_TRIGGER_PASS0_DSI_SAR_SAMPLE_DONE_LEVEL	pass[0].dsi_sar_sample_done
CYHAL_TRIGGER_PASS0_TR_SAR_OUT_EDGE	pass[0].tr_sar_out
CYHAL_TRIGGER_PASS0_TR_SAR_OUT_LEVEL	pass[0].tr_sar_out
CYHAL_TRIGGER_SCB0_TR_I2C_SCL_FILTERED	scb[0].tr_i2c_scl_filtered
CYHAL_TRIGGER_SCB1_TR_I2C_SCL_FILTERED	scb[1].tr_i2c_scl_filtered
CYHAL_TRIGGER_SCB2_TR_I2C_SCL_FILTERED	scb[2].tr_i2c_scl_filtered
CYHAL_TRIGGER_SCB3_TR_I2C_SCL_FILTERED	scb[3].tr_i2c_scl_filtered
CYHAL_TRIGGER_SCB4_TR_I2C_SCL_FILTERED	scb[4].tr_i2c_scl_filtered
CYHAL_TRIGGER_SCB0_TR_RX_REQ	scb[0].tr_rx_req
CYHAL_TRIGGER_SCB1_TR_RX_REQ	scb[1].tr_rx_req
CYHAL_TRIGGER_SCB2_TR_RX_REQ	scb[2].tr_rx_req
CYHAL_TRIGGER_SCB3_TR_RX_REQ	scb[3].tr_rx_req
CYHAL_TRIGGER_SCB4_TR_RX_REQ	scb[4].tr_rx_req
CYHAL_TRIGGER_SCB0_TR_TX_REQ	scb[0].tr_tx_req
CYHAL_TRIGGER_SCB1_TR_TX_REQ	scb[1].tr_tx_req
CYHAL_TRIGGER_SCB2_TR_TX_REQ	scb[2].tr_tx_req
CYHAL_TRIGGER_SCB3_TR_TX_REQ	scb[3].tr_tx_req
CYHAL_TRIGGER_SCB4_TR_TX_REQ	scb[4].tr_tx_req
CYHAL_TRIGGER_TCPWM_LINE0_EDGE	tcpwm.line[0]
CYHAL_TRIGGER_TCPWM_LINE0_LEVEL	tcpwm.line[0]
CYHAL_TRIGGER_TCPWM_LINE1_EDGE	tcpwm.line[1]
CYHAL_TRIGGER_TCPWM_LINE1_LEVEL	tcpwm.line[1]
CYHAL_TRIGGER_TCPWM_LINE2_EDGE	tcpwm.line[2]
CYHAL_TRIGGER_TCPWM_LINE2_LEVEL	tcpwm.line[2]
CYHAL_TRIGGER_TCPWM_LINE3_EDGE	tcpwm.line[3]
CYHAL_TRIGGER_TCPWM_LINE3_LEVEL	tcpwm.line[3]
CYHAL_TRIGGER_TCPWM_LINE4_EDGE	tcpwm.line[4]
CYHAL_TRIGGER_TCPWM_LINE4_LEVEL	tcpwm.line[4]
CYHAL_TRIGGER_TCPWM_LINE5_EDGE	tcpwm.line[5]
CYHAL_TRIGGER_TCPWM_LINE5_LEVEL	tcpwm.line[5]
CYHAL_TRIGGER_TCPWM_LINE6_EDGE	tcpwm.line[6]
CYHAL_TRIGGER_TCPWM_LINE6_LEVEL	tcpwm.line[6]
CYHAL_TRIGGER_TCPWM_LINE7_EDGE	tcpwm.line[7]
CYHAL_TRIGGER_TCPWM_LINE7_LEVEL	tcpwm.line[7]
CYHAL_TRIGGER_TCPWM_TR_COMPARE_MATCH0_EDGE	tcpwm.tr_compare_match[0]
CYHAL_TRIGGER_TCPWM_TR_COMPARE_MATCH0_LEVEL	tcpwm.tr_compare_match[0]
CYHAL_TRIGGER_TCPWM_TR_COMPARE_MATCH1_EDGE	tcpwm.tr_compare_match[1]
CYHAL_TRIGGER_TCPWM_TR_COMPARE_MATCH1_LEVEL	tcpwm.tr_compare_match[1]
CYHAL_TRIGGER_TCPWM_TR_COMPARE_MATCH2_EDGE	tcpwm.tr_compare_match[2]
CYHAL_TRIGGER_TCPWM_TR_COMPARE_MATCH2_LEVEL	tcpwm.tr_compare_match[2]
CYHAL_TRIGGER_TCPWM_TR_COMPARE_MATCH3_EDGE	tcpwm.tr_compare_match[3]
CYHAL_TRIGGER_TCPWM_TR_COMPARE_MATCH3_LEVEL	tcpwm.tr_compare_match[3]
CYHAL_TRIGGER_TCPWM_TR_COMPARE_MATCH4_EDGE	tcpwm.tr_compare_match[4]
CYHAL_TRIGGER_TCPWM_TR_COMPARE_MATCH4_LEVEL	tcpwm.tr_compare_match[4]
CYHAL_TRIGGER_TCPWM_TR_COMPARE_MATCH5_EDGE	tcpwm.tr_compare_match[5]
CYHAL_TRIGGER_TCPWM_TR_COMPARE_MATCH5_LEVEL	tcpwm.tr_compare_match[5]
CYHAL_TRIGGER_TCPWM_TR_COMPARE_MATCH6_EDGE	tcpwm.tr_compare_match[6]
CYHAL_TRIGGER_TCPWM_TR_COMPARE_MATCH6_LEVEL	tcpwm.tr_compare_match[6]
CYHAL_TRIGGER_TCPWM_TR_COMPARE_MATCH7_EDGE	tcpwm.tr_compare_match[7]
CYHAL_TRIGGER_TCPWM_TR_COMPARE_MATCH7_LEVEL	tcpwm.tr_compare_match[7]
CYHAL_TRIGGER_TCPWM_TR_OVERFLOW0_EDGE	tcpwm.tr_overflow[0]
CYHAL_TRIGGER_TCPWM_TR_OVERFLOW0_LEVEL	tcpwm.tr_overflow[0]
CYHAL_TRIGGER_TCPWM_TR_OVERFLOW1_EDGE	tcpwm.tr_overflow[1]
CYHAL_TRIGGER_TCPWM_TR_OVERFLOW1_LEVEL	tcpwm.tr_overflow[1]
CYHAL_TRIGGER_TCPWM_TR_OVERFLOW2_EDGE	tcpwm.tr_overflow[2]
CYHAL_TRIGGER_TCPWM_TR_OVERFLOW2_LEVEL	tcpwm.tr_overflow[2]
CYHAL_TRIGGER_TCPWM_TR_OVERFLOW3_EDGE	tcpwm.tr_overflow[3]
CYHAL_TRIGGER_TCPWM_TR_OVERFLOW3_LEVEL	tcpwm.tr_overflow[3]
CYHAL_TRIGGER_TCPWM_TR_OVERFLOW4_EDGE	tcpwm.tr_overflow[4]
CYHAL_TRIGGER_TCPWM_TR_OVERFLOW4_LEVEL	tcpwm.tr_overflow[4]
CYHAL_TRIGGER_TCPWM_TR_OVERFLOW5_EDGE	tcpwm.tr_overflow[5]
CYHAL_TRIGGER_TCPWM_TR_OVERFLOW5_LEVEL	tcpwm.tr_overflow[5]
CYHAL_TRIGGER_TCPWM_TR_OVERFLOW6_EDGE	tcpwm.tr_overflow[6]
CYHAL_TRIGGER_TCPWM_TR_OVERFLOW6_LEVEL	tcpwm.tr_overflow[6]
CYHAL_TRIGGER_TCPWM_TR_OVERFLOW7_EDGE	tcpwm.tr_overflow[7]
CYHAL_TRIGGER_TCPWM_TR_OVERFLOW7_LEVEL	tcpwm.tr_overflow[7]
CYHAL_TRIGGER_TCPWM_TR_UNDERFLOW0_EDGE	tcpwm.tr_underflow[0]
CYHAL_TRIGGER_TCPWM_TR_UNDERFLOW0_LEVEL	tcpwm.tr_underflow[0]
CYHAL_TRIGGER_TCPWM_TR_UNDERFLOW1_EDGE	tcpwm.tr_underflow[1]
CYHAL_TRIGGER_TCPWM_TR_UNDERFLOW1_LEVEL	tcpwm.tr_underflow[1]
CYHAL_TRIGGER_TCPWM_TR_UNDERFLOW2_EDGE	tcpwm.tr_underflow[2]
CYHAL_TRIGGER_TCPWM_TR_UNDERFLOW2_LEVEL	tcpwm.tr_underflow[2]
CYHAL_TRIGGER_TCPWM_TR_UNDERFLOW3_EDGE	tcpwm.tr_underflow[3]
CYHAL_TRIGGER_TCPWM_TR_UNDERFLOW3_LEVEL	tcpwm.tr_underflow[3]
CYHAL_TRIGGER_TCPWM_TR_UNDERFLOW4_EDGE	tcpwm.tr_underflow[4]
CYHAL_TRIGGER_TCPWM_TR_UNDERFLOW4_LEVEL	tcpwm.tr_underflow[4]
CYHAL_TRIGGER_TCPWM_TR_UNDERFLOW5_EDGE	tcpwm.tr_underflow[5]
CYHAL_TRIGGER_TCPWM_TR_UNDERFLOW5_LEVEL	tcpwm.tr_underflow[5]
CYHAL_TRIGGER_TCPWM_TR_UNDERFLOW6_EDGE	tcpwm.tr_underflow[6]
CYHAL_TRIGGER_TCPWM_TR_UNDERFLOW6_LEVEL	tcpwm.tr_underflow[6]
CYHAL_TRIGGER_TCPWM_TR_UNDERFLOW7_EDGE	tcpwm.tr_underflow[7]
CYHAL_TRIGGER_TCPWM_TR_UNDERFLOW7_LEVEL	tcpwm.tr_underflow[7]

cyhal_trigger_dest_psoc4100smax_t

enum cyhal_trigger_dest_psoc4100smax_t

Name of each output trigger.

Enumerator
CYHAL_TRIGGER_CANFD_TR_DBG_DMA_ACK0	DMA_Requests - canfd.tr_dbg_dma_ack[0].
CYHAL_TRIGGER_CANFD_TR_EVT_SWT_IN0	DMA_Requests - canfd.tr_evt_swt_in[0].
CYHAL_TRIGGER_CPUSS_DMAC_TR_IN0	DMA_Requests - cpuss.dmac_tr_in[0].
CYHAL_TRIGGER_CPUSS_DMAC_TR_IN1	DMA_Requests - cpuss.dmac_tr_in[1].
CYHAL_TRIGGER_CPUSS_DMAC_TR_IN2	DMA_Requests - cpuss.dmac_tr_in[2].
CYHAL_TRIGGER_CPUSS_DMAC_TR_IN3	DMA_Requests - cpuss.dmac_tr_in[3].
CYHAL_TRIGGER_CPUSS_DMAC_TR_IN4	DMA_Requests - cpuss.dmac_tr_in[4].
CYHAL_TRIGGER_CPUSS_DMAC_TR_IN5	DMA_Requests - cpuss.dmac_tr_in[5].
CYHAL_TRIGGER_CPUSS_DMAC_TR_IN6	DMA_Requests - cpuss.dmac_tr_in[6].
CYHAL_TRIGGER_CPUSS_DMAC_TR_IN7	DMA_Requests - cpuss.dmac_tr_in[7].
CYHAL_TRIGGER_CPUSS_DMAC_TR_IN8	DMA_Requests - cpuss.dmac_tr_in[8].
CYHAL_TRIGGER_CPUSS_DMAC_TR_IN9	DMA_Requests - cpuss.dmac_tr_in[9].
CYHAL_TRIGGER_CPUSS_DMAC_TR_IN10	DMA_Requests - cpuss.dmac_tr_in[10].
CYHAL_TRIGGER_CPUSS_DMAC_TR_IN11	DMA_Requests - cpuss.dmac_tr_in[11].
CYHAL_TRIGGER_CPUSS_DMAC_TR_IN12	DMA_Requests - cpuss.dmac_tr_in[12].
CYHAL_TRIGGER_CPUSS_DMAC_TR_IN13	DMA_Requests - cpuss.dmac_tr_in[13].
CYHAL_TRIGGER_CPUSS_DMAC_TR_IN14	DMA_Requests - cpuss.dmac_tr_in[14].
CYHAL_TRIGGER_CPUSS_DMAC_TR_IN15	DMA_Requests - cpuss.dmac_tr_in[15].
CYHAL_TRIGGER_MSC0_TR_RD_REQ_IN	CSD Triggers - msc[0].tr_rd_req_in.
CYHAL_TRIGGER_MSC1_TR_RD_REQ_IN	CSD Triggers - msc[1].tr_rd_req_in.
CYHAL_TRIGGER_MSC0_TR_WR_REQ_IN	CSD Triggers - msc[0].tr_wr_req_in.
CYHAL_TRIGGER_MSC1_TR_WR_REQ_IN	CSD Triggers - msc[1].tr_wr_req_in.
CYHAL_TRIGGER_PASS0_TR_SAR_IN	PASS Triggers - pass[0].tr_sar_in.
CYHAL_TRIGGER_TCPWM_TR_IN7	TCPWM Triggers - tcpwm.tr_in[7].
CYHAL_TRIGGER_TCPWM_TR_IN8	TCPWM Triggers - tcpwm.tr_in[8].
CYHAL_TRIGGER_TCPWM_TR_IN9	TCPWM Triggers - tcpwm.tr_in[9].
CYHAL_TRIGGER_TCPWM_TR_IN10	TCPWM Triggers - tcpwm.tr_in[10].
CYHAL_TRIGGER_TCPWM_TR_IN11	TCPWM Triggers - tcpwm.tr_in[11].
CYHAL_TRIGGER_TCPWM_TR_IN12	TCPWM Triggers - tcpwm.tr_in[12].
CYHAL_TRIGGER_TCPWM_TR_IN13	TCPWM Triggers - tcpwm.tr_in[13].