General Description

Trigger connections for psoc4100sp256kb.

Macros
#define	CYHAL_TRIGGER_CPUSS_ZERO (CYHAL_TRIGGER_CPUSS_ZERO_LEVEL)
	Deprecated defines for signals that can be either level or edge. More...

#define	CYHAL_TRIGGER_CPUSS_DMAC_TR_OUT0 (CYHAL_TRIGGER_CPUSS_DMAC_TR_OUT0_LEVEL)
	Legacy define. Instead, use the explicit _LEVEL or _EDGE version.

#define	CYHAL_TRIGGER_CPUSS_DMAC_TR_OUT1 (CYHAL_TRIGGER_CPUSS_DMAC_TR_OUT1_LEVEL)
	Legacy define. Instead, use the explicit _LEVEL or _EDGE version.

#define	CYHAL_TRIGGER_CPUSS_DMAC_TR_OUT2 (CYHAL_TRIGGER_CPUSS_DMAC_TR_OUT2_LEVEL)
	Legacy define. Instead, use the explicit _LEVEL or _EDGE version.

#define	CYHAL_TRIGGER_CPUSS_DMAC_TR_OUT3 (CYHAL_TRIGGER_CPUSS_DMAC_TR_OUT3_LEVEL)
	Legacy define. Instead, use the explicit _LEVEL or _EDGE version.

#define	CYHAL_TRIGGER_CPUSS_DMAC_TR_OUT4 (CYHAL_TRIGGER_CPUSS_DMAC_TR_OUT4_LEVEL)
	Legacy define. Instead, use the explicit _LEVEL or _EDGE version.

#define	CYHAL_TRIGGER_CPUSS_DMAC_TR_OUT5 (CYHAL_TRIGGER_CPUSS_DMAC_TR_OUT5_LEVEL)
	Legacy define. Instead, use the explicit _LEVEL or _EDGE version.

#define	CYHAL_TRIGGER_CPUSS_DMAC_TR_OUT6 (CYHAL_TRIGGER_CPUSS_DMAC_TR_OUT6_LEVEL)
	Legacy define. Instead, use the explicit _LEVEL or _EDGE version.

#define	CYHAL_TRIGGER_CPUSS_DMAC_TR_OUT7 (CYHAL_TRIGGER_CPUSS_DMAC_TR_OUT7_LEVEL)
	Legacy define. Instead, use the explicit _LEVEL or _EDGE version.

#define	CYHAL_TRIGGER_CSD_DSI_SENSE_OUT (CYHAL_TRIGGER_CSD_DSI_SENSE_OUT_LEVEL)
	Legacy define. Instead, use the explicit _LEVEL or _EDGE version.

#define	CYHAL_TRIGGER_CSD_TR_ADC_DONE (CYHAL_TRIGGER_CSD_TR_ADC_DONE_LEVEL)
	Legacy define. Instead, use the explicit _LEVEL or _EDGE version.

#define	CYHAL_TRIGGER_EXCO_TRIGGER (CYHAL_TRIGGER_EXCO_TRIGGER_LEVEL)
	Legacy define. Instead, use the explicit _LEVEL or _EDGE version.

#define	CYHAL_TRIGGER_LPCOMP_COMP_OUT0 (CYHAL_TRIGGER_LPCOMP_COMP_OUT0_LEVEL)
	Legacy define. Instead, use the explicit _LEVEL or _EDGE version.

#define	CYHAL_TRIGGER_LPCOMP_COMP_OUT1 (CYHAL_TRIGGER_LPCOMP_COMP_OUT1_LEVEL)
	Legacy define. Instead, use the explicit _LEVEL or _EDGE version.

#define	CYHAL_TRIGGER_PASS0_DSI_CTB_CMP0 (CYHAL_TRIGGER_PASS0_DSI_CTB_CMP0_LEVEL)
	Legacy define. Instead, use the explicit _LEVEL or _EDGE version.

#define	CYHAL_TRIGGER_PASS1_DSI_CTB_CMP0 (CYHAL_TRIGGER_PASS1_DSI_CTB_CMP0_LEVEL)
	Legacy define. Instead, use the explicit _LEVEL or _EDGE version.

#define	CYHAL_TRIGGER_PASS0_DSI_CTB_CMP1 (CYHAL_TRIGGER_PASS0_DSI_CTB_CMP1_LEVEL)
	Legacy define. Instead, use the explicit _LEVEL or _EDGE version.

#define	CYHAL_TRIGGER_PASS1_DSI_CTB_CMP1 (CYHAL_TRIGGER_PASS1_DSI_CTB_CMP1_LEVEL)
	Legacy define. Instead, use the explicit _LEVEL or _EDGE version.

#define	CYHAL_TRIGGER_PASS0_DSI_SAR_SAMPLE_DONE (CYHAL_TRIGGER_PASS0_DSI_SAR_SAMPLE_DONE_LEVEL)
	Legacy define. Instead, use the explicit _LEVEL or _EDGE version.

#define	CYHAL_TRIGGER_PASS1_DSI_SAR_SAMPLE_DONE (CYHAL_TRIGGER_PASS1_DSI_SAR_SAMPLE_DONE_LEVEL)
	Legacy define. Instead, use the explicit _LEVEL or _EDGE version.

#define	CYHAL_TRIGGER_PASS0_TR_SAR_OUT (CYHAL_TRIGGER_PASS0_TR_SAR_OUT_LEVEL)
	Legacy define. Instead, use the explicit _LEVEL or _EDGE version.

#define	CYHAL_TRIGGER_PASS1_TR_SAR_OUT (CYHAL_TRIGGER_PASS1_TR_SAR_OUT_LEVEL)
	Legacy define. Instead, use the explicit _LEVEL or _EDGE version.

#define	CYHAL_TRIGGER_SCB0_TR_RX_REQ (CYHAL_TRIGGER_SCB0_TR_RX_REQ_LEVEL)
	Legacy define. Instead, use the explicit _LEVEL or _EDGE version.

#define	CYHAL_TRIGGER_SCB1_TR_RX_REQ (CYHAL_TRIGGER_SCB1_TR_RX_REQ_LEVEL)
	Legacy define. Instead, use the explicit _LEVEL or _EDGE version.

#define	CYHAL_TRIGGER_SCB2_TR_RX_REQ (CYHAL_TRIGGER_SCB2_TR_RX_REQ_LEVEL)
	Legacy define. Instead, use the explicit _LEVEL or _EDGE version.

#define	CYHAL_TRIGGER_SCB3_TR_RX_REQ (CYHAL_TRIGGER_SCB3_TR_RX_REQ_LEVEL)
	Legacy define. Instead, use the explicit _LEVEL or _EDGE version.

#define	CYHAL_TRIGGER_SCB4_TR_RX_REQ (CYHAL_TRIGGER_SCB4_TR_RX_REQ_LEVEL)
	Legacy define. Instead, use the explicit _LEVEL or _EDGE version.

#define	CYHAL_TRIGGER_SCB0_TR_TX_REQ (CYHAL_TRIGGER_SCB0_TR_TX_REQ_LEVEL)
	Legacy define. Instead, use the explicit _LEVEL or _EDGE version.

#define	CYHAL_TRIGGER_SCB1_TR_TX_REQ (CYHAL_TRIGGER_SCB1_TR_TX_REQ_LEVEL)
	Legacy define. Instead, use the explicit _LEVEL or _EDGE version.

#define	CYHAL_TRIGGER_SCB2_TR_TX_REQ (CYHAL_TRIGGER_SCB2_TR_TX_REQ_LEVEL)
	Legacy define. Instead, use the explicit _LEVEL or _EDGE version.

#define	CYHAL_TRIGGER_SCB3_TR_TX_REQ (CYHAL_TRIGGER_SCB3_TR_TX_REQ_LEVEL)
	Legacy define. Instead, use the explicit _LEVEL or _EDGE version.

#define	CYHAL_TRIGGER_SCB4_TR_TX_REQ (CYHAL_TRIGGER_SCB4_TR_TX_REQ_LEVEL)
	Legacy define. Instead, use the explicit _LEVEL or _EDGE version.

#define	CYHAL_TRIGGER_TCPWM_LINE0 (CYHAL_TRIGGER_TCPWM_LINE0_LEVEL)
	Legacy define. Instead, use the explicit _LEVEL or _EDGE version.

#define	CYHAL_TRIGGER_TCPWM_LINE1 (CYHAL_TRIGGER_TCPWM_LINE1_LEVEL)
	Legacy define. Instead, use the explicit _LEVEL or _EDGE version.

#define	CYHAL_TRIGGER_TCPWM_LINE2 (CYHAL_TRIGGER_TCPWM_LINE2_LEVEL)
	Legacy define. Instead, use the explicit _LEVEL or _EDGE version.

#define	CYHAL_TRIGGER_TCPWM_LINE3 (CYHAL_TRIGGER_TCPWM_LINE3_LEVEL)
	Legacy define. Instead, use the explicit _LEVEL or _EDGE version.

#define	CYHAL_TRIGGER_TCPWM_LINE4 (CYHAL_TRIGGER_TCPWM_LINE4_LEVEL)
	Legacy define. Instead, use the explicit _LEVEL or _EDGE version.

#define	CYHAL_TRIGGER_TCPWM_LINE5 (CYHAL_TRIGGER_TCPWM_LINE5_LEVEL)
	Legacy define. Instead, use the explicit _LEVEL or _EDGE version.

#define	CYHAL_TRIGGER_TCPWM_LINE6 (CYHAL_TRIGGER_TCPWM_LINE6_LEVEL)
	Legacy define. Instead, use the explicit _LEVEL or _EDGE version.

#define	CYHAL_TRIGGER_TCPWM_LINE7 (CYHAL_TRIGGER_TCPWM_LINE7_LEVEL)
	Legacy define. Instead, use the explicit _LEVEL or _EDGE version.

#define	CYHAL_TRIGGER_TCPWM_TR_COMPARE_MATCH0 (CYHAL_TRIGGER_TCPWM_TR_COMPARE_MATCH0_LEVEL)
	Legacy define. Instead, use the explicit _LEVEL or _EDGE version.

#define	CYHAL_TRIGGER_TCPWM_TR_COMPARE_MATCH1 (CYHAL_TRIGGER_TCPWM_TR_COMPARE_MATCH1_LEVEL)
	Legacy define. Instead, use the explicit _LEVEL or _EDGE version.

#define	CYHAL_TRIGGER_TCPWM_TR_COMPARE_MATCH2 (CYHAL_TRIGGER_TCPWM_TR_COMPARE_MATCH2_LEVEL)
	Legacy define. Instead, use the explicit _LEVEL or _EDGE version.

#define	CYHAL_TRIGGER_TCPWM_TR_COMPARE_MATCH3 (CYHAL_TRIGGER_TCPWM_TR_COMPARE_MATCH3_LEVEL)
	Legacy define. Instead, use the explicit _LEVEL or _EDGE version.

#define	CYHAL_TRIGGER_TCPWM_TR_COMPARE_MATCH4 (CYHAL_TRIGGER_TCPWM_TR_COMPARE_MATCH4_LEVEL)
	Legacy define. Instead, use the explicit _LEVEL or _EDGE version.

#define	CYHAL_TRIGGER_TCPWM_TR_COMPARE_MATCH5 (CYHAL_TRIGGER_TCPWM_TR_COMPARE_MATCH5_LEVEL)
	Legacy define. Instead, use the explicit _LEVEL or _EDGE version.

#define	CYHAL_TRIGGER_TCPWM_TR_COMPARE_MATCH6 (CYHAL_TRIGGER_TCPWM_TR_COMPARE_MATCH6_LEVEL)
	Legacy define. Instead, use the explicit _LEVEL or _EDGE version.

#define	CYHAL_TRIGGER_TCPWM_TR_COMPARE_MATCH7 (CYHAL_TRIGGER_TCPWM_TR_COMPARE_MATCH7_LEVEL)
	Legacy define. Instead, use the explicit _LEVEL or _EDGE version.

#define	CYHAL_TRIGGER_TCPWM_TR_OVERFLOW0 (CYHAL_TRIGGER_TCPWM_TR_OVERFLOW0_LEVEL)
	Legacy define. Instead, use the explicit _LEVEL or _EDGE version.

#define	CYHAL_TRIGGER_TCPWM_TR_OVERFLOW1 (CYHAL_TRIGGER_TCPWM_TR_OVERFLOW1_LEVEL)
	Legacy define. Instead, use the explicit _LEVEL or _EDGE version.

#define	CYHAL_TRIGGER_TCPWM_TR_OVERFLOW2 (CYHAL_TRIGGER_TCPWM_TR_OVERFLOW2_LEVEL)
	Legacy define. Instead, use the explicit _LEVEL or _EDGE version.

#define	CYHAL_TRIGGER_TCPWM_TR_OVERFLOW3 (CYHAL_TRIGGER_TCPWM_TR_OVERFLOW3_LEVEL)
	Legacy define. Instead, use the explicit _LEVEL or _EDGE version.

#define	CYHAL_TRIGGER_TCPWM_TR_OVERFLOW4 (CYHAL_TRIGGER_TCPWM_TR_OVERFLOW4_LEVEL)
	Legacy define. Instead, use the explicit _LEVEL or _EDGE version.

#define	CYHAL_TRIGGER_TCPWM_TR_OVERFLOW5 (CYHAL_TRIGGER_TCPWM_TR_OVERFLOW5_LEVEL)
	Legacy define. Instead, use the explicit _LEVEL or _EDGE version.

#define	CYHAL_TRIGGER_TCPWM_TR_OVERFLOW6 (CYHAL_TRIGGER_TCPWM_TR_OVERFLOW6_LEVEL)
	Legacy define. Instead, use the explicit _LEVEL or _EDGE version.

#define	CYHAL_TRIGGER_TCPWM_TR_OVERFLOW7 (CYHAL_TRIGGER_TCPWM_TR_OVERFLOW7_LEVEL)
	Legacy define. Instead, use the explicit _LEVEL or _EDGE version.

#define	CYHAL_TRIGGER_TCPWM_TR_UNDERFLOW0 (CYHAL_TRIGGER_TCPWM_TR_UNDERFLOW0_LEVEL)
	Legacy define. Instead, use the explicit _LEVEL or _EDGE version.

#define	CYHAL_TRIGGER_TCPWM_TR_UNDERFLOW1 (CYHAL_TRIGGER_TCPWM_TR_UNDERFLOW1_LEVEL)
	Legacy define. Instead, use the explicit _LEVEL or _EDGE version.

#define	CYHAL_TRIGGER_TCPWM_TR_UNDERFLOW2 (CYHAL_TRIGGER_TCPWM_TR_UNDERFLOW2_LEVEL)
	Legacy define. Instead, use the explicit _LEVEL or _EDGE version.

#define	CYHAL_TRIGGER_TCPWM_TR_UNDERFLOW3 (CYHAL_TRIGGER_TCPWM_TR_UNDERFLOW3_LEVEL)
	Legacy define. Instead, use the explicit _LEVEL or _EDGE version.

#define	CYHAL_TRIGGER_TCPWM_TR_UNDERFLOW4 (CYHAL_TRIGGER_TCPWM_TR_UNDERFLOW4_LEVEL)
	Legacy define. Instead, use the explicit _LEVEL or _EDGE version.

#define	CYHAL_TRIGGER_TCPWM_TR_UNDERFLOW5 (CYHAL_TRIGGER_TCPWM_TR_UNDERFLOW5_LEVEL)
	Legacy define. Instead, use the explicit _LEVEL or _EDGE version.

#define	CYHAL_TRIGGER_TCPWM_TR_UNDERFLOW6 (CYHAL_TRIGGER_TCPWM_TR_UNDERFLOW6_LEVEL)
	Legacy define. Instead, use the explicit _LEVEL or _EDGE version.

#define	CYHAL_TRIGGER_TCPWM_TR_UNDERFLOW7 (CYHAL_TRIGGER_TCPWM_TR_UNDERFLOW7_LEVEL)
	Legacy define. Instead, use the explicit _LEVEL or _EDGE version.

Typedefs
typedef cyhal_trigger_source_psoc4100sp256kb_t	cyhal_source_t
	Typedef from device family specific trigger source to generic trigger source.

typedef cyhal_trigger_dest_psoc4100sp256kb_t	cyhal_dest_t
	Typedef from device family specific trigger dest to generic trigger dest.

Enumerations
enum	cyhal_trigger_source_psoc4100sp256kb_t { CYHAL_TRIGGER_CPUSS_ZERO_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_ZERO, CYHAL_SIGNAL_TYPE_EDGE), CYHAL_TRIGGER_CPUSS_ZERO_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_ZERO, CYHAL_SIGNAL_TYPE_LEVEL), CYHAL_TRIGGER_CPUSS_DMAC_TR_OUT0_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DMAC_TR_OUT0, CYHAL_SIGNAL_TYPE_EDGE), CYHAL_TRIGGER_CPUSS_DMAC_TR_OUT0_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DMAC_TR_OUT0, CYHAL_SIGNAL_TYPE_LEVEL), CYHAL_TRIGGER_CPUSS_DMAC_TR_OUT1_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DMAC_TR_OUT1, CYHAL_SIGNAL_TYPE_EDGE), CYHAL_TRIGGER_CPUSS_DMAC_TR_OUT1_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DMAC_TR_OUT1, CYHAL_SIGNAL_TYPE_LEVEL), CYHAL_TRIGGER_CPUSS_DMAC_TR_OUT2_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DMAC_TR_OUT2, CYHAL_SIGNAL_TYPE_EDGE), CYHAL_TRIGGER_CPUSS_DMAC_TR_OUT2_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DMAC_TR_OUT2, CYHAL_SIGNAL_TYPE_LEVEL), CYHAL_TRIGGER_CPUSS_DMAC_TR_OUT3_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DMAC_TR_OUT3, CYHAL_SIGNAL_TYPE_EDGE), CYHAL_TRIGGER_CPUSS_DMAC_TR_OUT3_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DMAC_TR_OUT3, CYHAL_SIGNAL_TYPE_LEVEL), CYHAL_TRIGGER_CPUSS_DMAC_TR_OUT4_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DMAC_TR_OUT4, CYHAL_SIGNAL_TYPE_EDGE), CYHAL_TRIGGER_CPUSS_DMAC_TR_OUT4_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DMAC_TR_OUT4, CYHAL_SIGNAL_TYPE_LEVEL), CYHAL_TRIGGER_CPUSS_DMAC_TR_OUT5_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DMAC_TR_OUT5, CYHAL_SIGNAL_TYPE_EDGE), CYHAL_TRIGGER_CPUSS_DMAC_TR_OUT5_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DMAC_TR_OUT5, CYHAL_SIGNAL_TYPE_LEVEL), CYHAL_TRIGGER_CPUSS_DMAC_TR_OUT6_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DMAC_TR_OUT6, CYHAL_SIGNAL_TYPE_EDGE), CYHAL_TRIGGER_CPUSS_DMAC_TR_OUT6_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DMAC_TR_OUT6, CYHAL_SIGNAL_TYPE_LEVEL), CYHAL_TRIGGER_CPUSS_DMAC_TR_OUT7_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DMAC_TR_OUT7, CYHAL_SIGNAL_TYPE_EDGE), CYHAL_TRIGGER_CPUSS_DMAC_TR_OUT7_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DMAC_TR_OUT7, CYHAL_SIGNAL_TYPE_LEVEL), CYHAL_TRIGGER_CSD_DSI_SENSE_OUT_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CSD_DSI_SENSE_OUT, CYHAL_SIGNAL_TYPE_EDGE), CYHAL_TRIGGER_CSD_DSI_SENSE_OUT_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CSD_DSI_SENSE_OUT, CYHAL_SIGNAL_TYPE_LEVEL), CYHAL_TRIGGER_CSD_TR_ADC_DONE_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CSD_TR_ADC_DONE, CYHAL_SIGNAL_TYPE_EDGE), CYHAL_TRIGGER_CSD_TR_ADC_DONE_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CSD_TR_ADC_DONE, CYHAL_SIGNAL_TYPE_LEVEL), CYHAL_TRIGGER_EXCO_TRIGGER_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_EXCO_TRIGGER, CYHAL_SIGNAL_TYPE_EDGE), CYHAL_TRIGGER_EXCO_TRIGGER_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_EXCO_TRIGGER, CYHAL_SIGNAL_TYPE_LEVEL), CYHAL_TRIGGER_LPCOMP_COMP_OUT0_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_LPCOMP_COMP_OUT0, CYHAL_SIGNAL_TYPE_EDGE), CYHAL_TRIGGER_LPCOMP_COMP_OUT0_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_LPCOMP_COMP_OUT0, CYHAL_SIGNAL_TYPE_LEVEL), CYHAL_TRIGGER_LPCOMP_COMP_OUT1_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_LPCOMP_COMP_OUT1, CYHAL_SIGNAL_TYPE_EDGE), CYHAL_TRIGGER_LPCOMP_COMP_OUT1_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_LPCOMP_COMP_OUT1, CYHAL_SIGNAL_TYPE_LEVEL), CYHAL_TRIGGER_PASS0_DSI_CTB_CMP0_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_DSI_CTB_CMP0, CYHAL_SIGNAL_TYPE_EDGE), CYHAL_TRIGGER_PASS0_DSI_CTB_CMP0_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_DSI_CTB_CMP0, CYHAL_SIGNAL_TYPE_LEVEL), CYHAL_TRIGGER_PASS1_DSI_CTB_CMP0_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS1_DSI_CTB_CMP0, CYHAL_SIGNAL_TYPE_EDGE), CYHAL_TRIGGER_PASS1_DSI_CTB_CMP0_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS1_DSI_CTB_CMP0, CYHAL_SIGNAL_TYPE_LEVEL), CYHAL_TRIGGER_PASS0_DSI_CTB_CMP1_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_DSI_CTB_CMP1, CYHAL_SIGNAL_TYPE_EDGE), CYHAL_TRIGGER_PASS0_DSI_CTB_CMP1_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_DSI_CTB_CMP1, CYHAL_SIGNAL_TYPE_LEVEL), CYHAL_TRIGGER_PASS1_DSI_CTB_CMP1_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS1_DSI_CTB_CMP1, CYHAL_SIGNAL_TYPE_EDGE), CYHAL_TRIGGER_PASS1_DSI_CTB_CMP1_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS1_DSI_CTB_CMP1, CYHAL_SIGNAL_TYPE_LEVEL), CYHAL_TRIGGER_PASS0_DSI_SAR_SAMPLE_DONE_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_DSI_SAR_SAMPLE_DONE, CYHAL_SIGNAL_TYPE_EDGE), CYHAL_TRIGGER_PASS0_DSI_SAR_SAMPLE_DONE_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_DSI_SAR_SAMPLE_DONE, CYHAL_SIGNAL_TYPE_LEVEL), CYHAL_TRIGGER_PASS1_DSI_SAR_SAMPLE_DONE_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS1_DSI_SAR_SAMPLE_DONE, CYHAL_SIGNAL_TYPE_EDGE), CYHAL_TRIGGER_PASS1_DSI_SAR_SAMPLE_DONE_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS1_DSI_SAR_SAMPLE_DONE, CYHAL_SIGNAL_TYPE_LEVEL), CYHAL_TRIGGER_PASS0_TR_SAR_OUT_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_OUT, CYHAL_SIGNAL_TYPE_EDGE), CYHAL_TRIGGER_PASS0_TR_SAR_OUT_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_OUT, CYHAL_SIGNAL_TYPE_LEVEL), CYHAL_TRIGGER_PASS1_TR_SAR_OUT_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS1_TR_SAR_OUT, CYHAL_SIGNAL_TYPE_EDGE), CYHAL_TRIGGER_PASS1_TR_SAR_OUT_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS1_TR_SAR_OUT, CYHAL_SIGNAL_TYPE_LEVEL), CYHAL_TRIGGER_SCB0_TR_RX_REQ_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_SCB0_TR_RX_REQ, CYHAL_SIGNAL_TYPE_EDGE), CYHAL_TRIGGER_SCB0_TR_RX_REQ_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_SCB0_TR_RX_REQ, CYHAL_SIGNAL_TYPE_LEVEL), CYHAL_TRIGGER_SCB1_TR_RX_REQ_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_SCB1_TR_RX_REQ, CYHAL_SIGNAL_TYPE_EDGE), CYHAL_TRIGGER_SCB1_TR_RX_REQ_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_SCB1_TR_RX_REQ, CYHAL_SIGNAL_TYPE_LEVEL), CYHAL_TRIGGER_SCB2_TR_RX_REQ_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_SCB2_TR_RX_REQ, CYHAL_SIGNAL_TYPE_EDGE), CYHAL_TRIGGER_SCB2_TR_RX_REQ_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_SCB2_TR_RX_REQ, CYHAL_SIGNAL_TYPE_LEVEL), CYHAL_TRIGGER_SCB3_TR_RX_REQ_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_SCB3_TR_RX_REQ, CYHAL_SIGNAL_TYPE_EDGE), CYHAL_TRIGGER_SCB3_TR_RX_REQ_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_SCB3_TR_RX_REQ, CYHAL_SIGNAL_TYPE_LEVEL), CYHAL_TRIGGER_SCB4_TR_RX_REQ_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_SCB4_TR_RX_REQ, CYHAL_SIGNAL_TYPE_EDGE), CYHAL_TRIGGER_SCB4_TR_RX_REQ_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_SCB4_TR_RX_REQ, CYHAL_SIGNAL_TYPE_LEVEL), CYHAL_TRIGGER_SCB0_TR_TX_REQ_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_SCB0_TR_TX_REQ, CYHAL_SIGNAL_TYPE_EDGE), CYHAL_TRIGGER_SCB0_TR_TX_REQ_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_SCB0_TR_TX_REQ, CYHAL_SIGNAL_TYPE_LEVEL), CYHAL_TRIGGER_SCB1_TR_TX_REQ_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_SCB1_TR_TX_REQ, CYHAL_SIGNAL_TYPE_EDGE), CYHAL_TRIGGER_SCB1_TR_TX_REQ_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_SCB1_TR_TX_REQ, CYHAL_SIGNAL_TYPE_LEVEL), CYHAL_TRIGGER_SCB2_TR_TX_REQ_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_SCB2_TR_TX_REQ, CYHAL_SIGNAL_TYPE_EDGE), CYHAL_TRIGGER_SCB2_TR_TX_REQ_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_SCB2_TR_TX_REQ, CYHAL_SIGNAL_TYPE_LEVEL), CYHAL_TRIGGER_SCB3_TR_TX_REQ_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_SCB3_TR_TX_REQ, CYHAL_SIGNAL_TYPE_EDGE), CYHAL_TRIGGER_SCB3_TR_TX_REQ_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_SCB3_TR_TX_REQ, CYHAL_SIGNAL_TYPE_LEVEL), CYHAL_TRIGGER_SCB4_TR_TX_REQ_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_SCB4_TR_TX_REQ, CYHAL_SIGNAL_TYPE_EDGE), CYHAL_TRIGGER_SCB4_TR_TX_REQ_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_SCB4_TR_TX_REQ, CYHAL_SIGNAL_TYPE_LEVEL), CYHAL_TRIGGER_TCPWM_LINE0_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM_LINE0, CYHAL_SIGNAL_TYPE_EDGE), CYHAL_TRIGGER_TCPWM_LINE0_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM_LINE0, CYHAL_SIGNAL_TYPE_LEVEL), CYHAL_TRIGGER_TCPWM_LINE1_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM_LINE1, CYHAL_SIGNAL_TYPE_EDGE), CYHAL_TRIGGER_TCPWM_LINE1_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM_LINE1, CYHAL_SIGNAL_TYPE_LEVEL), CYHAL_TRIGGER_TCPWM_LINE2_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM_LINE2, CYHAL_SIGNAL_TYPE_EDGE), CYHAL_TRIGGER_TCPWM_LINE2_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM_LINE2, CYHAL_SIGNAL_TYPE_LEVEL), CYHAL_TRIGGER_TCPWM_LINE3_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM_LINE3, CYHAL_SIGNAL_TYPE_EDGE), CYHAL_TRIGGER_TCPWM_LINE3_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM_LINE3, CYHAL_SIGNAL_TYPE_LEVEL), CYHAL_TRIGGER_TCPWM_LINE4_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM_LINE4, CYHAL_SIGNAL_TYPE_EDGE), CYHAL_TRIGGER_TCPWM_LINE4_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM_LINE4, CYHAL_SIGNAL_TYPE_LEVEL), CYHAL_TRIGGER_TCPWM_LINE5_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM_LINE5, CYHAL_SIGNAL_TYPE_EDGE), CYHAL_TRIGGER_TCPWM_LINE5_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM_LINE5, CYHAL_SIGNAL_TYPE_LEVEL), CYHAL_TRIGGER_TCPWM_LINE6_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM_LINE6, CYHAL_SIGNAL_TYPE_EDGE), CYHAL_TRIGGER_TCPWM_LINE6_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM_LINE6, CYHAL_SIGNAL_TYPE_LEVEL), CYHAL_TRIGGER_TCPWM_LINE7_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM_LINE7, CYHAL_SIGNAL_TYPE_EDGE), CYHAL_TRIGGER_TCPWM_LINE7_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM_LINE7, CYHAL_SIGNAL_TYPE_LEVEL), CYHAL_TRIGGER_TCPWM_TR_COMPARE_MATCH0_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM_TR_COMPARE_MATCH0, CYHAL_SIGNAL_TYPE_EDGE), CYHAL_TRIGGER_TCPWM_TR_COMPARE_MATCH0_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM_TR_COMPARE_MATCH0, CYHAL_SIGNAL_TYPE_LEVEL), CYHAL_TRIGGER_TCPWM_TR_COMPARE_MATCH1_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM_TR_COMPARE_MATCH1, CYHAL_SIGNAL_TYPE_EDGE), CYHAL_TRIGGER_TCPWM_TR_COMPARE_MATCH1_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM_TR_COMPARE_MATCH1, CYHAL_SIGNAL_TYPE_LEVEL), CYHAL_TRIGGER_TCPWM_TR_COMPARE_MATCH2_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM_TR_COMPARE_MATCH2, CYHAL_SIGNAL_TYPE_EDGE), CYHAL_TRIGGER_TCPWM_TR_COMPARE_MATCH2_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM_TR_COMPARE_MATCH2, CYHAL_SIGNAL_TYPE_LEVEL), CYHAL_TRIGGER_TCPWM_TR_COMPARE_MATCH3_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM_TR_COMPARE_MATCH3, CYHAL_SIGNAL_TYPE_EDGE), CYHAL_TRIGGER_TCPWM_TR_COMPARE_MATCH3_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM_TR_COMPARE_MATCH3, CYHAL_SIGNAL_TYPE_LEVEL), CYHAL_TRIGGER_TCPWM_TR_COMPARE_MATCH4_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM_TR_COMPARE_MATCH4, CYHAL_SIGNAL_TYPE_EDGE), CYHAL_TRIGGER_TCPWM_TR_COMPARE_MATCH4_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM_TR_COMPARE_MATCH4, CYHAL_SIGNAL_TYPE_LEVEL), CYHAL_TRIGGER_TCPWM_TR_COMPARE_MATCH5_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM_TR_COMPARE_MATCH5, CYHAL_SIGNAL_TYPE_EDGE), CYHAL_TRIGGER_TCPWM_TR_COMPARE_MATCH5_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM_TR_COMPARE_MATCH5, CYHAL_SIGNAL_TYPE_LEVEL), CYHAL_TRIGGER_TCPWM_TR_COMPARE_MATCH6_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM_TR_COMPARE_MATCH6, CYHAL_SIGNAL_TYPE_EDGE), CYHAL_TRIGGER_TCPWM_TR_COMPARE_MATCH6_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM_TR_COMPARE_MATCH6, CYHAL_SIGNAL_TYPE_LEVEL), CYHAL_TRIGGER_TCPWM_TR_COMPARE_MATCH7_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM_TR_COMPARE_MATCH7, CYHAL_SIGNAL_TYPE_EDGE), CYHAL_TRIGGER_TCPWM_TR_COMPARE_MATCH7_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM_TR_COMPARE_MATCH7, CYHAL_SIGNAL_TYPE_LEVEL), CYHAL_TRIGGER_TCPWM_TR_OVERFLOW0_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM_TR_OVERFLOW0, CYHAL_SIGNAL_TYPE_EDGE), CYHAL_TRIGGER_TCPWM_TR_OVERFLOW0_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM_TR_OVERFLOW0, CYHAL_SIGNAL_TYPE_LEVEL), CYHAL_TRIGGER_TCPWM_TR_OVERFLOW1_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM_TR_OVERFLOW1, CYHAL_SIGNAL_TYPE_EDGE), CYHAL_TRIGGER_TCPWM_TR_OVERFLOW1_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM_TR_OVERFLOW1, CYHAL_SIGNAL_TYPE_LEVEL), CYHAL_TRIGGER_TCPWM_TR_OVERFLOW2_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM_TR_OVERFLOW2, CYHAL_SIGNAL_TYPE_EDGE), CYHAL_TRIGGER_TCPWM_TR_OVERFLOW2_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM_TR_OVERFLOW2, CYHAL_SIGNAL_TYPE_LEVEL), CYHAL_TRIGGER_TCPWM_TR_OVERFLOW3_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM_TR_OVERFLOW3, CYHAL_SIGNAL_TYPE_EDGE), CYHAL_TRIGGER_TCPWM_TR_OVERFLOW3_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM_TR_OVERFLOW3, CYHAL_SIGNAL_TYPE_LEVEL), CYHAL_TRIGGER_TCPWM_TR_OVERFLOW4_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM_TR_OVERFLOW4, CYHAL_SIGNAL_TYPE_EDGE), CYHAL_TRIGGER_TCPWM_TR_OVERFLOW4_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM_TR_OVERFLOW4, CYHAL_SIGNAL_TYPE_LEVEL), CYHAL_TRIGGER_TCPWM_TR_OVERFLOW5_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM_TR_OVERFLOW5, CYHAL_SIGNAL_TYPE_EDGE), CYHAL_TRIGGER_TCPWM_TR_OVERFLOW5_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM_TR_OVERFLOW5, CYHAL_SIGNAL_TYPE_LEVEL), CYHAL_TRIGGER_TCPWM_TR_OVERFLOW6_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM_TR_OVERFLOW6, CYHAL_SIGNAL_TYPE_EDGE), CYHAL_TRIGGER_TCPWM_TR_OVERFLOW6_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM_TR_OVERFLOW6, CYHAL_SIGNAL_TYPE_LEVEL), CYHAL_TRIGGER_TCPWM_TR_OVERFLOW7_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM_TR_OVERFLOW7, CYHAL_SIGNAL_TYPE_EDGE), CYHAL_TRIGGER_TCPWM_TR_OVERFLOW7_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM_TR_OVERFLOW7, CYHAL_SIGNAL_TYPE_LEVEL), CYHAL_TRIGGER_TCPWM_TR_UNDERFLOW0_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM_TR_UNDERFLOW0, CYHAL_SIGNAL_TYPE_EDGE), CYHAL_TRIGGER_TCPWM_TR_UNDERFLOW0_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM_TR_UNDERFLOW0, CYHAL_SIGNAL_TYPE_LEVEL), CYHAL_TRIGGER_TCPWM_TR_UNDERFLOW1_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM_TR_UNDERFLOW1, CYHAL_SIGNAL_TYPE_EDGE), CYHAL_TRIGGER_TCPWM_TR_UNDERFLOW1_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM_TR_UNDERFLOW1, CYHAL_SIGNAL_TYPE_LEVEL), CYHAL_TRIGGER_TCPWM_TR_UNDERFLOW2_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM_TR_UNDERFLOW2, CYHAL_SIGNAL_TYPE_EDGE), CYHAL_TRIGGER_TCPWM_TR_UNDERFLOW2_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM_TR_UNDERFLOW2, CYHAL_SIGNAL_TYPE_LEVEL), CYHAL_TRIGGER_TCPWM_TR_UNDERFLOW3_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM_TR_UNDERFLOW3, CYHAL_SIGNAL_TYPE_EDGE), CYHAL_TRIGGER_TCPWM_TR_UNDERFLOW3_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM_TR_UNDERFLOW3, CYHAL_SIGNAL_TYPE_LEVEL), CYHAL_TRIGGER_TCPWM_TR_UNDERFLOW4_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM_TR_UNDERFLOW4, CYHAL_SIGNAL_TYPE_EDGE), CYHAL_TRIGGER_TCPWM_TR_UNDERFLOW4_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM_TR_UNDERFLOW4, CYHAL_SIGNAL_TYPE_LEVEL), CYHAL_TRIGGER_TCPWM_TR_UNDERFLOW5_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM_TR_UNDERFLOW5, CYHAL_SIGNAL_TYPE_EDGE), CYHAL_TRIGGER_TCPWM_TR_UNDERFLOW5_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM_TR_UNDERFLOW5, CYHAL_SIGNAL_TYPE_LEVEL), CYHAL_TRIGGER_TCPWM_TR_UNDERFLOW6_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM_TR_UNDERFLOW6, CYHAL_SIGNAL_TYPE_EDGE), CYHAL_TRIGGER_TCPWM_TR_UNDERFLOW6_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM_TR_UNDERFLOW6, CYHAL_SIGNAL_TYPE_LEVEL), CYHAL_TRIGGER_TCPWM_TR_UNDERFLOW7_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM_TR_UNDERFLOW7, CYHAL_SIGNAL_TYPE_EDGE), CYHAL_TRIGGER_TCPWM_TR_UNDERFLOW7_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM_TR_UNDERFLOW7, CYHAL_SIGNAL_TYPE_LEVEL) }
	Name of each input trigger. More...

enum	cyhal_trigger_dest_psoc4100sp256kb_t { CYHAL_TRIGGER_CPUSS_DMAC_TR_IN0 = 0, CYHAL_TRIGGER_CPUSS_DMAC_TR_IN1 = 1, CYHAL_TRIGGER_CPUSS_DMAC_TR_IN2 = 2, CYHAL_TRIGGER_CPUSS_DMAC_TR_IN3 = 3, CYHAL_TRIGGER_CPUSS_DMAC_TR_IN4 = 4, CYHAL_TRIGGER_CPUSS_DMAC_TR_IN5 = 5, CYHAL_TRIGGER_CPUSS_DMAC_TR_IN6 = 6, CYHAL_TRIGGER_CPUSS_DMAC_TR_IN7 = 7, CYHAL_TRIGGER_CSD_DSI_START = 8, CYHAL_TRIGGER_PASS0_TR_SAR_IN = 9, CYHAL_TRIGGER_PASS1_TR_SAR_IN = 10, CYHAL_TRIGGER_TCPWM_TR_IN7 = 11, CYHAL_TRIGGER_TCPWM_TR_IN8 = 12, CYHAL_TRIGGER_TCPWM_TR_IN9 = 13, CYHAL_TRIGGER_TCPWM_TR_IN10 = 14, CYHAL_TRIGGER_TCPWM_TR_IN11 = 15, CYHAL_TRIGGER_TCPWM_TR_IN12 = 16, CYHAL_TRIGGER_TCPWM_TR_IN13 = 17 }
	Name of each output trigger. More...

Macro Definition Documentation

◆ CYHAL_TRIGGER_CPUSS_ZERO

#define CYHAL_TRIGGER_CPUSS_ZERO (CYHAL_TRIGGER_CPUSS_ZERO_LEVEL)

Deprecated defines for signals that can be either level or edge.

Legacy define. Instead, use the explicit _LEVEL or _EDGE version.

Enumeration Type Documentation

◆ cyhal_trigger_source_psoc4100sp256kb_t

enum cyhal_trigger_source_psoc4100sp256kb_t

Name of each input trigger.

Enumerator
CYHAL_TRIGGER_CPUSS_ZERO_EDGE	cpuss.zero
CYHAL_TRIGGER_CPUSS_ZERO_LEVEL	cpuss.zero
CYHAL_TRIGGER_CPUSS_DMAC_TR_OUT0_EDGE	cpuss.dmac_tr_out[0]
CYHAL_TRIGGER_CPUSS_DMAC_TR_OUT0_LEVEL	cpuss.dmac_tr_out[0]
CYHAL_TRIGGER_CPUSS_DMAC_TR_OUT1_EDGE	cpuss.dmac_tr_out[1]
CYHAL_TRIGGER_CPUSS_DMAC_TR_OUT1_LEVEL	cpuss.dmac_tr_out[1]
CYHAL_TRIGGER_CPUSS_DMAC_TR_OUT2_EDGE	cpuss.dmac_tr_out[2]
CYHAL_TRIGGER_CPUSS_DMAC_TR_OUT2_LEVEL	cpuss.dmac_tr_out[2]
CYHAL_TRIGGER_CPUSS_DMAC_TR_OUT3_EDGE	cpuss.dmac_tr_out[3]
CYHAL_TRIGGER_CPUSS_DMAC_TR_OUT3_LEVEL	cpuss.dmac_tr_out[3]
CYHAL_TRIGGER_CPUSS_DMAC_TR_OUT4_EDGE	cpuss.dmac_tr_out[4]
CYHAL_TRIGGER_CPUSS_DMAC_TR_OUT4_LEVEL	cpuss.dmac_tr_out[4]
CYHAL_TRIGGER_CPUSS_DMAC_TR_OUT5_EDGE	cpuss.dmac_tr_out[5]
CYHAL_TRIGGER_CPUSS_DMAC_TR_OUT5_LEVEL	cpuss.dmac_tr_out[5]
CYHAL_TRIGGER_CPUSS_DMAC_TR_OUT6_EDGE	cpuss.dmac_tr_out[6]
CYHAL_TRIGGER_CPUSS_DMAC_TR_OUT6_LEVEL	cpuss.dmac_tr_out[6]
CYHAL_TRIGGER_CPUSS_DMAC_TR_OUT7_EDGE	cpuss.dmac_tr_out[7]
CYHAL_TRIGGER_CPUSS_DMAC_TR_OUT7_LEVEL	cpuss.dmac_tr_out[7]
CYHAL_TRIGGER_CSD_DSI_SENSE_OUT_EDGE	csd.dsi_sense_out
CYHAL_TRIGGER_CSD_DSI_SENSE_OUT_LEVEL	csd.dsi_sense_out
CYHAL_TRIGGER_CSD_TR_ADC_DONE_EDGE	csd.tr_adc_done
CYHAL_TRIGGER_CSD_TR_ADC_DONE_LEVEL	csd.tr_adc_done
CYHAL_TRIGGER_EXCO_TRIGGER_EDGE	exco.trigger
CYHAL_TRIGGER_EXCO_TRIGGER_LEVEL	exco.trigger
CYHAL_TRIGGER_LPCOMP_COMP_OUT0_EDGE	lpcomp.comp_out[0]
CYHAL_TRIGGER_LPCOMP_COMP_OUT0_LEVEL	lpcomp.comp_out[0]
CYHAL_TRIGGER_LPCOMP_COMP_OUT1_EDGE	lpcomp.comp_out[1]
CYHAL_TRIGGER_LPCOMP_COMP_OUT1_LEVEL	lpcomp.comp_out[1]
CYHAL_TRIGGER_PASS0_DSI_CTB_CMP0_EDGE	pass[0].dsi_ctb_cmp0
CYHAL_TRIGGER_PASS0_DSI_CTB_CMP0_LEVEL	pass[0].dsi_ctb_cmp0
CYHAL_TRIGGER_PASS1_DSI_CTB_CMP0_EDGE	pass[1].dsi_ctb_cmp0
CYHAL_TRIGGER_PASS1_DSI_CTB_CMP0_LEVEL	pass[1].dsi_ctb_cmp0
CYHAL_TRIGGER_PASS0_DSI_CTB_CMP1_EDGE	pass[0].dsi_ctb_cmp1
CYHAL_TRIGGER_PASS0_DSI_CTB_CMP1_LEVEL	pass[0].dsi_ctb_cmp1
CYHAL_TRIGGER_PASS1_DSI_CTB_CMP1_EDGE	pass[1].dsi_ctb_cmp1
CYHAL_TRIGGER_PASS1_DSI_CTB_CMP1_LEVEL	pass[1].dsi_ctb_cmp1
CYHAL_TRIGGER_PASS0_DSI_SAR_SAMPLE_DONE_EDGE	pass[0].dsi_sar_sample_done
CYHAL_TRIGGER_PASS0_DSI_SAR_SAMPLE_DONE_LEVEL	pass[0].dsi_sar_sample_done
CYHAL_TRIGGER_PASS1_DSI_SAR_SAMPLE_DONE_EDGE	pass[1].dsi_sar_sample_done
CYHAL_TRIGGER_PASS1_DSI_SAR_SAMPLE_DONE_LEVEL	pass[1].dsi_sar_sample_done
CYHAL_TRIGGER_PASS0_TR_SAR_OUT_EDGE	pass[0].tr_sar_out
CYHAL_TRIGGER_PASS0_TR_SAR_OUT_LEVEL	pass[0].tr_sar_out
CYHAL_TRIGGER_PASS1_TR_SAR_OUT_EDGE	pass[1].tr_sar_out
CYHAL_TRIGGER_PASS1_TR_SAR_OUT_LEVEL	pass[1].tr_sar_out
CYHAL_TRIGGER_SCB0_TR_RX_REQ_EDGE	scb[0].tr_rx_req
CYHAL_TRIGGER_SCB0_TR_RX_REQ_LEVEL	scb[0].tr_rx_req
CYHAL_TRIGGER_SCB1_TR_RX_REQ_EDGE	scb[1].tr_rx_req
CYHAL_TRIGGER_SCB1_TR_RX_REQ_LEVEL	scb[1].tr_rx_req
CYHAL_TRIGGER_SCB2_TR_RX_REQ_EDGE	scb[2].tr_rx_req
CYHAL_TRIGGER_SCB2_TR_RX_REQ_LEVEL	scb[2].tr_rx_req
CYHAL_TRIGGER_SCB3_TR_RX_REQ_EDGE	scb[3].tr_rx_req
CYHAL_TRIGGER_SCB3_TR_RX_REQ_LEVEL	scb[3].tr_rx_req
CYHAL_TRIGGER_SCB4_TR_RX_REQ_EDGE	scb[4].tr_rx_req
CYHAL_TRIGGER_SCB4_TR_RX_REQ_LEVEL	scb[4].tr_rx_req
CYHAL_TRIGGER_SCB0_TR_TX_REQ_EDGE	scb[0].tr_tx_req
CYHAL_TRIGGER_SCB0_TR_TX_REQ_LEVEL	scb[0].tr_tx_req
CYHAL_TRIGGER_SCB1_TR_TX_REQ_EDGE	scb[1].tr_tx_req
CYHAL_TRIGGER_SCB1_TR_TX_REQ_LEVEL	scb[1].tr_tx_req
CYHAL_TRIGGER_SCB2_TR_TX_REQ_EDGE	scb[2].tr_tx_req
CYHAL_TRIGGER_SCB2_TR_TX_REQ_LEVEL	scb[2].tr_tx_req
CYHAL_TRIGGER_SCB3_TR_TX_REQ_EDGE	scb[3].tr_tx_req
CYHAL_TRIGGER_SCB3_TR_TX_REQ_LEVEL	scb[3].tr_tx_req
CYHAL_TRIGGER_SCB4_TR_TX_REQ_EDGE	scb[4].tr_tx_req
CYHAL_TRIGGER_SCB4_TR_TX_REQ_LEVEL	scb[4].tr_tx_req
CYHAL_TRIGGER_TCPWM_LINE0_EDGE	tcpwm.line[0]
CYHAL_TRIGGER_TCPWM_LINE0_LEVEL	tcpwm.line[0]
CYHAL_TRIGGER_TCPWM_LINE1_EDGE	tcpwm.line[1]
CYHAL_TRIGGER_TCPWM_LINE1_LEVEL	tcpwm.line[1]
CYHAL_TRIGGER_TCPWM_LINE2_EDGE	tcpwm.line[2]
CYHAL_TRIGGER_TCPWM_LINE2_LEVEL	tcpwm.line[2]
CYHAL_TRIGGER_TCPWM_LINE3_EDGE	tcpwm.line[3]
CYHAL_TRIGGER_TCPWM_LINE3_LEVEL	tcpwm.line[3]
CYHAL_TRIGGER_TCPWM_LINE4_EDGE	tcpwm.line[4]
CYHAL_TRIGGER_TCPWM_LINE4_LEVEL	tcpwm.line[4]
CYHAL_TRIGGER_TCPWM_LINE5_EDGE	tcpwm.line[5]
CYHAL_TRIGGER_TCPWM_LINE5_LEVEL	tcpwm.line[5]
CYHAL_TRIGGER_TCPWM_LINE6_EDGE	tcpwm.line[6]
CYHAL_TRIGGER_TCPWM_LINE6_LEVEL	tcpwm.line[6]
CYHAL_TRIGGER_TCPWM_LINE7_EDGE	tcpwm.line[7]
CYHAL_TRIGGER_TCPWM_LINE7_LEVEL	tcpwm.line[7]
CYHAL_TRIGGER_TCPWM_TR_COMPARE_MATCH0_EDGE	tcpwm.tr_compare_match[0]
CYHAL_TRIGGER_TCPWM_TR_COMPARE_MATCH0_LEVEL	tcpwm.tr_compare_match[0]
CYHAL_TRIGGER_TCPWM_TR_COMPARE_MATCH1_EDGE	tcpwm.tr_compare_match[1]
CYHAL_TRIGGER_TCPWM_TR_COMPARE_MATCH1_LEVEL	tcpwm.tr_compare_match[1]
CYHAL_TRIGGER_TCPWM_TR_COMPARE_MATCH2_EDGE	tcpwm.tr_compare_match[2]
CYHAL_TRIGGER_TCPWM_TR_COMPARE_MATCH2_LEVEL	tcpwm.tr_compare_match[2]
CYHAL_TRIGGER_TCPWM_TR_COMPARE_MATCH3_EDGE	tcpwm.tr_compare_match[3]
CYHAL_TRIGGER_TCPWM_TR_COMPARE_MATCH3_LEVEL	tcpwm.tr_compare_match[3]
CYHAL_TRIGGER_TCPWM_TR_COMPARE_MATCH4_EDGE	tcpwm.tr_compare_match[4]
CYHAL_TRIGGER_TCPWM_TR_COMPARE_MATCH4_LEVEL	tcpwm.tr_compare_match[4]
CYHAL_TRIGGER_TCPWM_TR_COMPARE_MATCH5_EDGE	tcpwm.tr_compare_match[5]
CYHAL_TRIGGER_TCPWM_TR_COMPARE_MATCH5_LEVEL	tcpwm.tr_compare_match[5]
CYHAL_TRIGGER_TCPWM_TR_COMPARE_MATCH6_EDGE	tcpwm.tr_compare_match[6]
CYHAL_TRIGGER_TCPWM_TR_COMPARE_MATCH6_LEVEL	tcpwm.tr_compare_match[6]
CYHAL_TRIGGER_TCPWM_TR_COMPARE_MATCH7_EDGE	tcpwm.tr_compare_match[7]
CYHAL_TRIGGER_TCPWM_TR_COMPARE_MATCH7_LEVEL	tcpwm.tr_compare_match[7]
CYHAL_TRIGGER_TCPWM_TR_OVERFLOW0_EDGE	tcpwm.tr_overflow[0]
CYHAL_TRIGGER_TCPWM_TR_OVERFLOW0_LEVEL	tcpwm.tr_overflow[0]
CYHAL_TRIGGER_TCPWM_TR_OVERFLOW1_EDGE	tcpwm.tr_overflow[1]
CYHAL_TRIGGER_TCPWM_TR_OVERFLOW1_LEVEL	tcpwm.tr_overflow[1]
CYHAL_TRIGGER_TCPWM_TR_OVERFLOW2_EDGE	tcpwm.tr_overflow[2]
CYHAL_TRIGGER_TCPWM_TR_OVERFLOW2_LEVEL	tcpwm.tr_overflow[2]
CYHAL_TRIGGER_TCPWM_TR_OVERFLOW3_EDGE	tcpwm.tr_overflow[3]
CYHAL_TRIGGER_TCPWM_TR_OVERFLOW3_LEVEL	tcpwm.tr_overflow[3]
CYHAL_TRIGGER_TCPWM_TR_OVERFLOW4_EDGE	tcpwm.tr_overflow[4]
CYHAL_TRIGGER_TCPWM_TR_OVERFLOW4_LEVEL	tcpwm.tr_overflow[4]
CYHAL_TRIGGER_TCPWM_TR_OVERFLOW5_EDGE	tcpwm.tr_overflow[5]
CYHAL_TRIGGER_TCPWM_TR_OVERFLOW5_LEVEL	tcpwm.tr_overflow[5]
CYHAL_TRIGGER_TCPWM_TR_OVERFLOW6_EDGE	tcpwm.tr_overflow[6]
CYHAL_TRIGGER_TCPWM_TR_OVERFLOW6_LEVEL	tcpwm.tr_overflow[6]
CYHAL_TRIGGER_TCPWM_TR_OVERFLOW7_EDGE	tcpwm.tr_overflow[7]
CYHAL_TRIGGER_TCPWM_TR_OVERFLOW7_LEVEL	tcpwm.tr_overflow[7]
CYHAL_TRIGGER_TCPWM_TR_UNDERFLOW0_EDGE	tcpwm.tr_underflow[0]
CYHAL_TRIGGER_TCPWM_TR_UNDERFLOW0_LEVEL	tcpwm.tr_underflow[0]
CYHAL_TRIGGER_TCPWM_TR_UNDERFLOW1_EDGE	tcpwm.tr_underflow[1]
CYHAL_TRIGGER_TCPWM_TR_UNDERFLOW1_LEVEL	tcpwm.tr_underflow[1]
CYHAL_TRIGGER_TCPWM_TR_UNDERFLOW2_EDGE	tcpwm.tr_underflow[2]
CYHAL_TRIGGER_TCPWM_TR_UNDERFLOW2_LEVEL	tcpwm.tr_underflow[2]
CYHAL_TRIGGER_TCPWM_TR_UNDERFLOW3_EDGE	tcpwm.tr_underflow[3]
CYHAL_TRIGGER_TCPWM_TR_UNDERFLOW3_LEVEL	tcpwm.tr_underflow[3]
CYHAL_TRIGGER_TCPWM_TR_UNDERFLOW4_EDGE	tcpwm.tr_underflow[4]
CYHAL_TRIGGER_TCPWM_TR_UNDERFLOW4_LEVEL	tcpwm.tr_underflow[4]
CYHAL_TRIGGER_TCPWM_TR_UNDERFLOW5_EDGE	tcpwm.tr_underflow[5]
CYHAL_TRIGGER_TCPWM_TR_UNDERFLOW5_LEVEL	tcpwm.tr_underflow[5]
CYHAL_TRIGGER_TCPWM_TR_UNDERFLOW6_EDGE	tcpwm.tr_underflow[6]
CYHAL_TRIGGER_TCPWM_TR_UNDERFLOW6_LEVEL	tcpwm.tr_underflow[6]
CYHAL_TRIGGER_TCPWM_TR_UNDERFLOW7_EDGE	tcpwm.tr_underflow[7]
CYHAL_TRIGGER_TCPWM_TR_UNDERFLOW7_LEVEL	tcpwm.tr_underflow[7]

◆ cyhal_trigger_dest_psoc4100sp256kb_t

enum cyhal_trigger_dest_psoc4100sp256kb_t

Name of each output trigger.

Enumerator
CYHAL_TRIGGER_CPUSS_DMAC_TR_IN0	GP_DMA_Requests - cpuss.dmac_tr_in[0].
CYHAL_TRIGGER_CPUSS_DMAC_TR_IN1	GP_DMA_Requests - cpuss.dmac_tr_in[1].
CYHAL_TRIGGER_CPUSS_DMAC_TR_IN2	GP_DMA_Requests - cpuss.dmac_tr_in[2].
CYHAL_TRIGGER_CPUSS_DMAC_TR_IN3	GP_DMA_Requests - cpuss.dmac_tr_in[3].
CYHAL_TRIGGER_CPUSS_DMAC_TR_IN4	GP_DMA_Requests - cpuss.dmac_tr_in[4].
CYHAL_TRIGGER_CPUSS_DMAC_TR_IN5	GP_DMA_Requests - cpuss.dmac_tr_in[5].
CYHAL_TRIGGER_CPUSS_DMAC_TR_IN6	GP_DMA_Requests - cpuss.dmac_tr_in[6].
CYHAL_TRIGGER_CPUSS_DMAC_TR_IN7	GP_DMA_Requests - cpuss.dmac_tr_in[7].
CYHAL_TRIGGER_CSD_DSI_START	CSD Trigger Mux - csd.dsi_start.
CYHAL_TRIGGER_PASS0_TR_SAR_IN	PASS[0] Triggers - pass[0].tr_sar_in.
CYHAL_TRIGGER_PASS1_TR_SAR_IN	PASS[1] Triggers - pass[1].tr_sar_in.
CYHAL_TRIGGER_TCPWM_TR_IN7	TCPWM Triggers - tcpwm.tr_in[7].
CYHAL_TRIGGER_TCPWM_TR_IN8	TCPWM Triggers - tcpwm.tr_in[8].
CYHAL_TRIGGER_TCPWM_TR_IN9	TCPWM Triggers - tcpwm.tr_in[9].
CYHAL_TRIGGER_TCPWM_TR_IN10	TCPWM Triggers - tcpwm.tr_in[10].
CYHAL_TRIGGER_TCPWM_TR_IN11	TCPWM Triggers - tcpwm.tr_in[11].
CYHAL_TRIGGER_TCPWM_TR_IN12	TCPWM Triggers - tcpwm.tr_in[12].
CYHAL_TRIGGER_TCPWM_TR_IN13	TCPWM Triggers - tcpwm.tr_in[13].

General Description

Macros

Typedefs

Enumerations

Macro Definition Documentation

◆ CYHAL_TRIGGER_CPUSS_ZERO

Enumeration Type Documentation

◆ cyhal_trigger_source_psoc4100sp256kb_t

◆ cyhal_trigger_dest_psoc4100sp256kb_t