General Description

Trigger connections for ccg7s.

Macros
#define	CYHAL_TRIGGER_CPUSS_ZERO (CYHAL_TRIGGER_CPUSS_ZERO_LEVEL)
	Deprecated defines for signals that can be either level or edge. More...

#define	CYHAL_TRIGGER_PASS0_DSI_SAR_SAMPLE_DONE (CYHAL_TRIGGER_PASS0_DSI_SAR_SAMPLE_DONE_LEVEL)
	Legacy define. Instead, use the explicit _LEVEL or _EDGE version.

#define	CYHAL_TRIGGER_PASS0_TR_SAR_OUT (CYHAL_TRIGGER_PASS0_TR_SAR_OUT_LEVEL)
	Legacy define. Instead, use the explicit _LEVEL or _EDGE version.

#define	CYHAL_TRIGGER_TCPWM_TR_COMPARE_MATCH0 (CYHAL_TRIGGER_TCPWM_TR_COMPARE_MATCH0_LEVEL)
	Legacy define. Instead, use the explicit _LEVEL or _EDGE version.

#define	CYHAL_TRIGGER_TCPWM_TR_COMPARE_MATCH1 (CYHAL_TRIGGER_TCPWM_TR_COMPARE_MATCH1_LEVEL)
	Legacy define. Instead, use the explicit _LEVEL or _EDGE version.

#define	CYHAL_TRIGGER_TCPWM_TR_COMPARE_MATCH2 (CYHAL_TRIGGER_TCPWM_TR_COMPARE_MATCH2_LEVEL)
	Legacy define. Instead, use the explicit _LEVEL or _EDGE version.

#define	CYHAL_TRIGGER_TCPWM_TR_COMPARE_MATCH3 (CYHAL_TRIGGER_TCPWM_TR_COMPARE_MATCH3_LEVEL)
	Legacy define. Instead, use the explicit _LEVEL or _EDGE version.

#define	CYHAL_TRIGGER_TCPWM_TR_OVERFLOW0 (CYHAL_TRIGGER_TCPWM_TR_OVERFLOW0_LEVEL)
	Legacy define. Instead, use the explicit _LEVEL or _EDGE version.

#define	CYHAL_TRIGGER_TCPWM_TR_OVERFLOW1 (CYHAL_TRIGGER_TCPWM_TR_OVERFLOW1_LEVEL)
	Legacy define. Instead, use the explicit _LEVEL or _EDGE version.

#define	CYHAL_TRIGGER_TCPWM_TR_OVERFLOW2 (CYHAL_TRIGGER_TCPWM_TR_OVERFLOW2_LEVEL)
	Legacy define. Instead, use the explicit _LEVEL or _EDGE version.

#define	CYHAL_TRIGGER_TCPWM_TR_OVERFLOW3 (CYHAL_TRIGGER_TCPWM_TR_OVERFLOW3_LEVEL)
	Legacy define. Instead, use the explicit _LEVEL or _EDGE version.

#define	CYHAL_TRIGGER_TCPWM_TR_UNDERFLOW0 (CYHAL_TRIGGER_TCPWM_TR_UNDERFLOW0_LEVEL)
	Legacy define. Instead, use the explicit _LEVEL or _EDGE version.

#define	CYHAL_TRIGGER_TCPWM_TR_UNDERFLOW1 (CYHAL_TRIGGER_TCPWM_TR_UNDERFLOW1_LEVEL)
	Legacy define. Instead, use the explicit _LEVEL or _EDGE version.

#define	CYHAL_TRIGGER_TCPWM_TR_UNDERFLOW2 (CYHAL_TRIGGER_TCPWM_TR_UNDERFLOW2_LEVEL)
	Legacy define. Instead, use the explicit _LEVEL or _EDGE version.

#define	CYHAL_TRIGGER_TCPWM_TR_UNDERFLOW3 (CYHAL_TRIGGER_TCPWM_TR_UNDERFLOW3_LEVEL)
	Legacy define. Instead, use the explicit _LEVEL or _EDGE version.

#define	CYHAL_TRIGGER_USBPD0_TR_OUT_0 (CYHAL_TRIGGER_USBPD0_TR_OUT_0_LEVEL)
	Legacy define. Instead, use the explicit _LEVEL or _EDGE version.

#define	CYHAL_TRIGGER_USBPD0_TR_OUT_1 (CYHAL_TRIGGER_USBPD0_TR_OUT_1_LEVEL)
	Legacy define. Instead, use the explicit _LEVEL or _EDGE version.

#define	CYHAL_TRIGGER_USBPD0_TR_OUT_2 (CYHAL_TRIGGER_USBPD0_TR_OUT_2_LEVEL)
	Legacy define. Instead, use the explicit _LEVEL or _EDGE version.

#define	CYHAL_TRIGGER_USBPD0_TR_OUT_3 (CYHAL_TRIGGER_USBPD0_TR_OUT_3_LEVEL)
	Legacy define. Instead, use the explicit _LEVEL or _EDGE version.

#define	CYHAL_TRIGGER_USBPD0_TR_OUT_4 (CYHAL_TRIGGER_USBPD0_TR_OUT_4_LEVEL)
	Legacy define. Instead, use the explicit _LEVEL or _EDGE version.

#define	CYHAL_TRIGGER_USBPD0_TR_OUT_5 (CYHAL_TRIGGER_USBPD0_TR_OUT_5_LEVEL)
	Legacy define. Instead, use the explicit _LEVEL or _EDGE version.

#define	CYHAL_TRIGGER_USBPD0_TR_OUT_6 (CYHAL_TRIGGER_USBPD0_TR_OUT_6_LEVEL)
	Legacy define. Instead, use the explicit _LEVEL or _EDGE version.

Typedefs
typedef cyhal_trigger_source_ccg7s_t	cyhal_source_t
	Typedef from device family specific trigger source to generic trigger source.

typedef cyhal_trigger_dest_ccg7s_t	cyhal_dest_t
	Typedef from device family specific trigger dest to generic trigger dest.

Enumerations
enum	cyhal_trigger_source_ccg7s_t { CYHAL_TRIGGER_CPUSS_ZERO_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_ZERO, CYHAL_SIGNAL_TYPE_EDGE), CYHAL_TRIGGER_CPUSS_ZERO_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_ZERO, CYHAL_SIGNAL_TYPE_LEVEL), CYHAL_TRIGGER_PASS0_DSI_SAR_SAMPLE_DONE_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_DSI_SAR_SAMPLE_DONE, CYHAL_SIGNAL_TYPE_EDGE), CYHAL_TRIGGER_PASS0_DSI_SAR_SAMPLE_DONE_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_DSI_SAR_SAMPLE_DONE, CYHAL_SIGNAL_TYPE_LEVEL), CYHAL_TRIGGER_PASS0_TR_SAR_OUT_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_OUT, CYHAL_SIGNAL_TYPE_EDGE), CYHAL_TRIGGER_PASS0_TR_SAR_OUT_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_OUT, CYHAL_SIGNAL_TYPE_LEVEL), CYHAL_TRIGGER_TCPWM_TR_COMPARE_MATCH0_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM_TR_COMPARE_MATCH0, CYHAL_SIGNAL_TYPE_EDGE), CYHAL_TRIGGER_TCPWM_TR_COMPARE_MATCH0_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM_TR_COMPARE_MATCH0, CYHAL_SIGNAL_TYPE_LEVEL), CYHAL_TRIGGER_TCPWM_TR_COMPARE_MATCH1_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM_TR_COMPARE_MATCH1, CYHAL_SIGNAL_TYPE_EDGE), CYHAL_TRIGGER_TCPWM_TR_COMPARE_MATCH1_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM_TR_COMPARE_MATCH1, CYHAL_SIGNAL_TYPE_LEVEL), CYHAL_TRIGGER_TCPWM_TR_COMPARE_MATCH2_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM_TR_COMPARE_MATCH2, CYHAL_SIGNAL_TYPE_EDGE), CYHAL_TRIGGER_TCPWM_TR_COMPARE_MATCH2_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM_TR_COMPARE_MATCH2, CYHAL_SIGNAL_TYPE_LEVEL), CYHAL_TRIGGER_TCPWM_TR_COMPARE_MATCH3_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM_TR_COMPARE_MATCH3, CYHAL_SIGNAL_TYPE_EDGE), CYHAL_TRIGGER_TCPWM_TR_COMPARE_MATCH3_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM_TR_COMPARE_MATCH3, CYHAL_SIGNAL_TYPE_LEVEL), CYHAL_TRIGGER_TCPWM_TR_OVERFLOW0_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM_TR_OVERFLOW0, CYHAL_SIGNAL_TYPE_EDGE), CYHAL_TRIGGER_TCPWM_TR_OVERFLOW0_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM_TR_OVERFLOW0, CYHAL_SIGNAL_TYPE_LEVEL), CYHAL_TRIGGER_TCPWM_TR_OVERFLOW1_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM_TR_OVERFLOW1, CYHAL_SIGNAL_TYPE_EDGE), CYHAL_TRIGGER_TCPWM_TR_OVERFLOW1_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM_TR_OVERFLOW1, CYHAL_SIGNAL_TYPE_LEVEL), CYHAL_TRIGGER_TCPWM_TR_OVERFLOW2_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM_TR_OVERFLOW2, CYHAL_SIGNAL_TYPE_EDGE), CYHAL_TRIGGER_TCPWM_TR_OVERFLOW2_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM_TR_OVERFLOW2, CYHAL_SIGNAL_TYPE_LEVEL), CYHAL_TRIGGER_TCPWM_TR_OVERFLOW3_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM_TR_OVERFLOW3, CYHAL_SIGNAL_TYPE_EDGE), CYHAL_TRIGGER_TCPWM_TR_OVERFLOW3_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM_TR_OVERFLOW3, CYHAL_SIGNAL_TYPE_LEVEL), CYHAL_TRIGGER_TCPWM_TR_UNDERFLOW0_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM_TR_UNDERFLOW0, CYHAL_SIGNAL_TYPE_EDGE), CYHAL_TRIGGER_TCPWM_TR_UNDERFLOW0_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM_TR_UNDERFLOW0, CYHAL_SIGNAL_TYPE_LEVEL), CYHAL_TRIGGER_TCPWM_TR_UNDERFLOW1_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM_TR_UNDERFLOW1, CYHAL_SIGNAL_TYPE_EDGE), CYHAL_TRIGGER_TCPWM_TR_UNDERFLOW1_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM_TR_UNDERFLOW1, CYHAL_SIGNAL_TYPE_LEVEL), CYHAL_TRIGGER_TCPWM_TR_UNDERFLOW2_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM_TR_UNDERFLOW2, CYHAL_SIGNAL_TYPE_EDGE), CYHAL_TRIGGER_TCPWM_TR_UNDERFLOW2_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM_TR_UNDERFLOW2, CYHAL_SIGNAL_TYPE_LEVEL), CYHAL_TRIGGER_TCPWM_TR_UNDERFLOW3_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM_TR_UNDERFLOW3, CYHAL_SIGNAL_TYPE_EDGE), CYHAL_TRIGGER_TCPWM_TR_UNDERFLOW3_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM_TR_UNDERFLOW3, CYHAL_SIGNAL_TYPE_LEVEL), CYHAL_TRIGGER_USBPD0_TR_OUT_0_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_USBPD0_TR_OUT_0, CYHAL_SIGNAL_TYPE_EDGE), CYHAL_TRIGGER_USBPD0_TR_OUT_0_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_USBPD0_TR_OUT_0, CYHAL_SIGNAL_TYPE_LEVEL), CYHAL_TRIGGER_USBPD0_TR_OUT_1_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_USBPD0_TR_OUT_1, CYHAL_SIGNAL_TYPE_EDGE), CYHAL_TRIGGER_USBPD0_TR_OUT_1_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_USBPD0_TR_OUT_1, CYHAL_SIGNAL_TYPE_LEVEL), CYHAL_TRIGGER_USBPD0_TR_OUT_2_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_USBPD0_TR_OUT_2, CYHAL_SIGNAL_TYPE_EDGE), CYHAL_TRIGGER_USBPD0_TR_OUT_2_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_USBPD0_TR_OUT_2, CYHAL_SIGNAL_TYPE_LEVEL), CYHAL_TRIGGER_USBPD0_TR_OUT_3_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_USBPD0_TR_OUT_3, CYHAL_SIGNAL_TYPE_EDGE), CYHAL_TRIGGER_USBPD0_TR_OUT_3_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_USBPD0_TR_OUT_3, CYHAL_SIGNAL_TYPE_LEVEL), CYHAL_TRIGGER_USBPD0_TR_OUT_4_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_USBPD0_TR_OUT_4, CYHAL_SIGNAL_TYPE_EDGE), CYHAL_TRIGGER_USBPD0_TR_OUT_4_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_USBPD0_TR_OUT_4, CYHAL_SIGNAL_TYPE_LEVEL), CYHAL_TRIGGER_USBPD0_TR_OUT_5_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_USBPD0_TR_OUT_5, CYHAL_SIGNAL_TYPE_EDGE), CYHAL_TRIGGER_USBPD0_TR_OUT_5_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_USBPD0_TR_OUT_5, CYHAL_SIGNAL_TYPE_LEVEL), CYHAL_TRIGGER_USBPD0_TR_OUT_6_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_USBPD0_TR_OUT_6, CYHAL_SIGNAL_TYPE_EDGE), CYHAL_TRIGGER_USBPD0_TR_OUT_6_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_USBPD0_TR_OUT_6, CYHAL_SIGNAL_TYPE_LEVEL) }
	Name of each input trigger. More...

enum	cyhal_trigger_dest_ccg7s_t { CYHAL_TRIGGER_PASS0_TR_SAR_IN = 0, CYHAL_TRIGGER_TCPWM_TR_IN8 = 1, CYHAL_TRIGGER_TCPWM_TR_IN9 = 2, CYHAL_TRIGGER_TCPWM_TR_IN10 = 3, CYHAL_TRIGGER_TCPWM_TR_IN11 = 4, CYHAL_TRIGGER_TCPWM_TR_IN12 = 5, CYHAL_TRIGGER_TCPWM_TR_IN13 = 6 }
	Name of each output trigger. More...

Macro Definition Documentation

◆ CYHAL_TRIGGER_CPUSS_ZERO

#define CYHAL_TRIGGER_CPUSS_ZERO (CYHAL_TRIGGER_CPUSS_ZERO_LEVEL)

Deprecated defines for signals that can be either level or edge.

Legacy define. Instead, use the explicit _LEVEL or _EDGE version.

Enumeration Type Documentation

◆ cyhal_trigger_source_ccg7s_t

enum cyhal_trigger_source_ccg7s_t

Name of each input trigger.

Enumerator
CYHAL_TRIGGER_CPUSS_ZERO_EDGE	cpuss.zero
CYHAL_TRIGGER_CPUSS_ZERO_LEVEL	cpuss.zero
CYHAL_TRIGGER_PASS0_DSI_SAR_SAMPLE_DONE_EDGE	pass[0].dsi_sar_sample_done
CYHAL_TRIGGER_PASS0_DSI_SAR_SAMPLE_DONE_LEVEL	pass[0].dsi_sar_sample_done
CYHAL_TRIGGER_PASS0_TR_SAR_OUT_EDGE	pass[0].tr_sar_out
CYHAL_TRIGGER_PASS0_TR_SAR_OUT_LEVEL	pass[0].tr_sar_out
CYHAL_TRIGGER_TCPWM_TR_COMPARE_MATCH0_EDGE	tcpwm.tr_compare_match[0]
CYHAL_TRIGGER_TCPWM_TR_COMPARE_MATCH0_LEVEL	tcpwm.tr_compare_match[0]
CYHAL_TRIGGER_TCPWM_TR_COMPARE_MATCH1_EDGE	tcpwm.tr_compare_match[1]
CYHAL_TRIGGER_TCPWM_TR_COMPARE_MATCH1_LEVEL	tcpwm.tr_compare_match[1]
CYHAL_TRIGGER_TCPWM_TR_COMPARE_MATCH2_EDGE	tcpwm.tr_compare_match[2]
CYHAL_TRIGGER_TCPWM_TR_COMPARE_MATCH2_LEVEL	tcpwm.tr_compare_match[2]
CYHAL_TRIGGER_TCPWM_TR_COMPARE_MATCH3_EDGE	tcpwm.tr_compare_match[3]
CYHAL_TRIGGER_TCPWM_TR_COMPARE_MATCH3_LEVEL	tcpwm.tr_compare_match[3]
CYHAL_TRIGGER_TCPWM_TR_OVERFLOW0_EDGE	tcpwm.tr_overflow[0]
CYHAL_TRIGGER_TCPWM_TR_OVERFLOW0_LEVEL	tcpwm.tr_overflow[0]
CYHAL_TRIGGER_TCPWM_TR_OVERFLOW1_EDGE	tcpwm.tr_overflow[1]
CYHAL_TRIGGER_TCPWM_TR_OVERFLOW1_LEVEL	tcpwm.tr_overflow[1]
CYHAL_TRIGGER_TCPWM_TR_OVERFLOW2_EDGE	tcpwm.tr_overflow[2]
CYHAL_TRIGGER_TCPWM_TR_OVERFLOW2_LEVEL	tcpwm.tr_overflow[2]
CYHAL_TRIGGER_TCPWM_TR_OVERFLOW3_EDGE	tcpwm.tr_overflow[3]
CYHAL_TRIGGER_TCPWM_TR_OVERFLOW3_LEVEL	tcpwm.tr_overflow[3]
CYHAL_TRIGGER_TCPWM_TR_UNDERFLOW0_EDGE	tcpwm.tr_underflow[0]
CYHAL_TRIGGER_TCPWM_TR_UNDERFLOW0_LEVEL	tcpwm.tr_underflow[0]
CYHAL_TRIGGER_TCPWM_TR_UNDERFLOW1_EDGE	tcpwm.tr_underflow[1]
CYHAL_TRIGGER_TCPWM_TR_UNDERFLOW1_LEVEL	tcpwm.tr_underflow[1]
CYHAL_TRIGGER_TCPWM_TR_UNDERFLOW2_EDGE	tcpwm.tr_underflow[2]
CYHAL_TRIGGER_TCPWM_TR_UNDERFLOW2_LEVEL	tcpwm.tr_underflow[2]
CYHAL_TRIGGER_TCPWM_TR_UNDERFLOW3_EDGE	tcpwm.tr_underflow[3]
CYHAL_TRIGGER_TCPWM_TR_UNDERFLOW3_LEVEL	tcpwm.tr_underflow[3]
CYHAL_TRIGGER_USBPD0_TR_OUT_0_EDGE	usbpd[0].tr_out_0
CYHAL_TRIGGER_USBPD0_TR_OUT_0_LEVEL	usbpd[0].tr_out_0
CYHAL_TRIGGER_USBPD0_TR_OUT_1_EDGE	usbpd[0].tr_out_1
CYHAL_TRIGGER_USBPD0_TR_OUT_1_LEVEL	usbpd[0].tr_out_1
CYHAL_TRIGGER_USBPD0_TR_OUT_2_EDGE	usbpd[0].tr_out_2
CYHAL_TRIGGER_USBPD0_TR_OUT_2_LEVEL	usbpd[0].tr_out_2
CYHAL_TRIGGER_USBPD0_TR_OUT_3_EDGE	usbpd[0].tr_out_3
CYHAL_TRIGGER_USBPD0_TR_OUT_3_LEVEL	usbpd[0].tr_out_3
CYHAL_TRIGGER_USBPD0_TR_OUT_4_EDGE	usbpd[0].tr_out_4
CYHAL_TRIGGER_USBPD0_TR_OUT_4_LEVEL	usbpd[0].tr_out_4
CYHAL_TRIGGER_USBPD0_TR_OUT_5_EDGE	usbpd[0].tr_out_5
CYHAL_TRIGGER_USBPD0_TR_OUT_5_LEVEL	usbpd[0].tr_out_5
CYHAL_TRIGGER_USBPD0_TR_OUT_6_EDGE	usbpd[0].tr_out_6
CYHAL_TRIGGER_USBPD0_TR_OUT_6_LEVEL	usbpd[0].tr_out_6

◆ cyhal_trigger_dest_ccg7s_t

enum cyhal_trigger_dest_ccg7s_t

Name of each output trigger.

Enumerator
CYHAL_TRIGGER_PASS0_TR_SAR_IN	PASS Triggers - pass[0].tr_sar_in.
CYHAL_TRIGGER_TCPWM_TR_IN8	TCPWM Triggers - tcpwm.tr_in[8].
CYHAL_TRIGGER_TCPWM_TR_IN9	TCPWM Triggers - tcpwm.tr_in[9].
CYHAL_TRIGGER_TCPWM_TR_IN10	TCPWM Triggers - tcpwm.tr_in[10].
CYHAL_TRIGGER_TCPWM_TR_IN11	TCPWM Triggers - tcpwm.tr_in[11].
CYHAL_TRIGGER_TCPWM_TR_IN12	TCPWM Triggers - tcpwm.tr_in[12].
CYHAL_TRIGGER_TCPWM_TR_IN13	TCPWM Triggers - tcpwm.tr_in[13].

General Description

Macros

Typedefs

Enumerations

Macro Definition Documentation

◆ CYHAL_TRIGGER_CPUSS_ZERO

Enumeration Type Documentation

◆ cyhal_trigger_source_ccg7s_t

◆ cyhal_trigger_dest_ccg7s_t