Data Structures

General Description

Data Structures
struct	cy_stc_pll_config_t
	Structure containing information for configuration of a PLL. More...
struct	cy_stc_dpll_lp_config_t
	Structure containing information for configuration of a DPLL-LP. More...
struct	cy_stc_dpll_hp_config_t
	Structure containing information for configuration of a DPLL-HP. More...
struct	cy_stc_pll_manual_config_t
	Structure containing information for manual configuration of a PLL. More...

Enumerations
enum	cy_en_wait_mode_select_t {   CY_SYSCLK_DPLL_HP_CLK4MHZ_1US_CNT_VAL = 0U ,   CY_SYSCLK_DPLL_HP_CLK10MHZ_1US_CNT_VAL = 1U ,   CY_SYSCLK_DPLL_HP_CLK15MHZ_1US_CNT_VAL = 2U ,   CY_SYSCLK_DPLL_HP_CLK20MHZ_1US_CNT_VAL = 3U ,   CY_SYSCLK_DPLL_HP_CLK30MHZ_1US_CNT_VAL = 4U ,   CY_SYSCLK_DPLL_HP_CLK40MHZ_1US_CNT_VAL = 5U ,   CY_SYSCLK_DPLL_HP_CLK45MHZ_1US_CNT_VAL = 6U ,   CY_SYSCLK_DPLL_HP_CLK50MHZ_1US_CNT_VAL = 7U }
	DPLL-HP wait mode selection enum. More...

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Data Structure Documentation

cy_stc_pll_config_t

struct cy_stc_pll_config_t

Data Fields
uint32_t	inputFreq	frequency of PLL source, in Hz
uint32_t	outputFreq	frequency of PLL output, in Hz
bool	lfMode	CLK_PLL_CONFIG register, PLL_LF_MODE bit.
cy_en_fll_pll_output_mode_t	outputMode	CLK_PLL_CONFIG register, BYPASS_SEL bits.

cy_stc_dpll_lp_config_t

struct cy_stc_dpll_lp_config_t

Data Fields
uint8_t	feedbackDiv	CONFIG register, FEEDBACK_DIV (P) bits.
uint8_t	referenceDiv	CONFIG register, REFERENCE_DIV (Q) bits.
uint8_t	outputDiv	CONFIG register, OUTPUT_DIV bits.
bool	pllDcoMode	CONFIG register, PLL_DCO_MODE bit.
cy_en_fll_pll_output_mode_t	outputMode	CONFIG register, BYPASS_SEL bits.
uint32_t	fracDiv	CONFIG2 register, FRAC_DIV bits.
bool	fracDitherEn	CONFIG2 register, FRAC_DITHER_EN bit.
bool	fracEn	CONFIG2 register, FRAC_EN bit.
uint32_t	sscgDepth	CONFIG3 register, SSCG_DEPTH bits.
uint8_t	sscgRate	CONFIG3 register, SSCG_RATE bits.
bool	sscgDitherEn	CONFIG3 register, SSCG_DITHER_EN bit.
bool	sscgMode	CONFIG3 register, SSCG_MODE bit.
bool	sscgEn	CONFIG3 register, SSCG_EN bit.
uint32_t	dcoCode	CONFIG4 register, DCO_CODE bits.
bool	disableBias	CONFIG4 register, PLL_CS_PB2_DIS bit.
uint32_t	pllTg	CONFIG4 register, TG_MODE bits.
uint32_t	kiInt	CONFIG5 register, Gain of P/I loop filter integrator path for INT operation.
uint32_t	kpInt	CONFIG5 register, Gain of P/I loop filter integrator path for INT operation.
uint32_t	kiAccInt	CONFIG5 register, KI_ACC_INT bits.
uint32_t	kpAccInt	CONFIG5 register, KP_ACC_INT bits.
uint32_t	pwrupAccInt	CONFIG5 register, PWRUP_ACC_INT bits.
uint32_t	kiFrac	CONFIG5 register, Gain of P/I loop filter proportional path for FRACT operation.
uint32_t	kpFrac	CONFIG5 register, Gain of P/I loop filter integrator path for FRACT operation.
uint32_t	kiAccFrac	CONFIG6 register, KI_ACC_FRACT bits.
uint32_t	kpAccFrac	CONFIG7 register, KP_ACC_FRACT bits.
uint32_t	pwrupAccFrac	CONFIG5 register, PWRUP_ACC_INT bits, only for SRSS_1_1.
uint32_t	kiSscg	CONFIG5 register, Gain of P/I loop filter proportional path for SSCG operation.
uint32_t	kpSscg	CONFIG5 register, Gain of P/I loop filter integrator path for SSCG operation.
uint32_t	kiAccSscg	CONFIG7 register, KI_ACC_SSCG bits.
uint32_t	kpAccSscg	CONFIG7 register, KP_ACC_SSCG bits.
uint32_t	pwrupAccSscg	CONFIG7 register, KP_ACC_SSCG bits.

cy_stc_dpll_hp_config_t

struct cy_stc_dpll_hp_config_t

Data Fields
uint8_t	nDiv	CONFIG register, NDIV bits, Ratio between DCO frequency and reference frequency.
uint8_t	pDiv	CONFIG register, PDIV bits, Pre-Divider for scaling the reference frequency.
uint8_t	kDiv	CONFIG register, KDIV bits, Post-Divider.
cy_en_fll_pll_output_mode_t	outputMode	CONFIG register, BYPASS_SEL bits.
bool	pllEn	CONFIG register, ENABLE bits, Master Enable for PLL.
uint32_t	nDivFract	CONFIG2 register, NDIV_FRACT bits, N-divider division factor.
cy_en_wait_mode_select_t	freqModeSel	CONFIG2 register, MODE_SEL bits, Selects the waiting time for Power Initialization sequence.
uint8_t	ivrTrim	CONFIG2 register, IVR_TRIM bits, Trim value for the Regulated Voltage.
bool	clkrSel	CONFIG3 register, CLKR_SEL bit, Select re-timed reference clock.
bool	fdsmSel	CONFIG3 register, FDSM_SEL bit, DSM clock division select, true - div_by_2, false - div_by_4.
uint8_t	alphaCoarse	CONFIG4 register, LF_LC_ALPHA bits, Alpha value of the coarse filter.
uint8_t	betaCoarse	CONFIG4 register, LF_LC_BETA bits, Beta value of the coarse filter.
uint8_t	flockThresh	CONFIG4 register, FLOCK_EN_THRESH bits, PQDIFF threshold under which FINE Filtering gets enabled.
uint8_t	flockWait	CONFIG4 register, FLOCK_WAITPER bits, Period over which flock_en_thresh must be met in order for FINE Filtering enabling.
uint8_t	flockLkThres	CONFIG4 register, FLOCK_LK_THRESH bits, PQDIFF threshold under which DLL asserts Freq LOCK.
uint8_t	flockLkWait	CONFIG4 register, FLOCK_LK_WAITPER bits, Period over which flock_en_thresh must be met in order for Freq Locking.
uint8_t	flockObs	CONFIG4 register, FLOCK_OBSWIN bits, Period over which PQDIFF is computed/observed.
uint8_t	alphaExt	CONFIG5 register, LF_ALPHA bits, External Alpha value.
uint8_t	betaExt	CONFIG5 register, LF_BETA bits, External Beta value.
bool	lfEn	CONFIG5 register, LF_SET_PARAMS bit, enable for external loop filter control (alpha and beta values)
uint16_t	dtCal	CONFIG5 register, DUTY CAL circuit status.
uint16_t	tmodFreq	TRIGMOD register, TRIMOD_FREQ bits, Triangular-Frequency Modulation: modulation frequency.
uint16_t	tmodGrad	TRIGMOD register, TRIMOD_GRD bits, Triangular-Frequency Modulation: modulation gradient.
uint32_t	tmodRate	TRIGMOD2 register, TRIMOD_RATE bits, Triangular-Frequency Modulation Rate.
bool	tmodEn	TRIGMOD2 register, TRIMOD_EN bit, Triangular-Frequency Modulation enable.
bool	tmodStop	TRIGMOD2 register, TRIMOD_STP bit, Triangular-Frequency Modulation stop.
bool	pllLocked	STATUS register, LOCKED bits, PLL Lock Indicator.
bool	pllUnlock	STATUS register, UNLOCK_OCCURRED bit, Sets whenever the PLL Lock bit goes low, and stays set until cleared by firmware.
bool	lockDetReset	STATUS register, LOCKDET_RES bit, Restart lock detector.
bool	lockDetRstAck	STATUS register, LOCKDET_RES_ACK bit, Acknowledgement for lock detection restart.
uint8_t	dcCalDelta	DUTYCAL_CTRL register, DELTA bits, Margins for the duty cycle calibration error
bool	dcRatioStatus	DUTYCAL_CTRL register, RATIO_OK bit, Status of the duty calibration ratio.
bool	dcStatus	DUTYCAL_CTRL register, OK bit, Status of the duty calibration.
uint16_t	dcTarget	DUTYCAL_CTRL register, TARGET bits, Duty cycle target
bool	dcEnRingOsc	DUTYCAL_CTRL register, CTRL_RG_EN bit, Enables ring oscillator for duty cycle digitization.
bool	dcEn	DUTYCAL_CTRL register, EN bit, Enables duty cycle calibration.

cy_stc_pll_manual_config_t

struct cy_stc_pll_manual_config_t

Data Fields
cy_stc_dpll_lp_config_t *	lpPllCfg	DPLL-LP configuration.
cy_stc_dpll_hp_config_t *	hpPllCfg	DPLL-HP configuration.

Enumeration Type Documentation

cy_en_wait_mode_select_t

enum cy_en_wait_mode_select_t

DPLL-HP wait mode selection enum.

See CONFIG2 register, bits MODE_SEL.

Enumerator
CY_SYSCLK_DPLL_HP_CLK4MHZ_1US_CNT_VAL	clk_dig frequency = 4MHz
CY_SYSCLK_DPLL_HP_CLK10MHZ_1US_CNT_VAL	clk_dig frequency = 10MHz
CY_SYSCLK_DPLL_HP_CLK15MHZ_1US_CNT_VAL	clk_dig frequency = 15MHz
CY_SYSCLK_DPLL_HP_CLK20MHZ_1US_CNT_VAL	clk_dig frequency = 20MHz
CY_SYSCLK_DPLL_HP_CLK30MHZ_1US_CNT_VAL	clk_dig frequency = 30MHz
CY_SYSCLK_DPLL_HP_CLK40MHZ_1US_CNT_VAL	clk_dig frequency = 40MHz
CY_SYSCLK_DPLL_HP_CLK45MHZ_1US_CNT_VAL	clk_dig frequency = 45MHz
CY_SYSCLK_DPLL_HP_CLK50MHZ_1US_CNT_VAL	clk_dig frequency = 50MHz