General Description

Enumerations
enum	cy_en_fll_pll_output_mode_t { CY_SYSCLK_FLLPLL_OUTPUT_AUTO = 0U , CY_SYSCLK_FLLPLL_OUTPUT_AUTO1 = 1U , CY_SYSCLK_FLLPLL_OUTPUT_INPUT = 2U , CY_SYSCLK_FLLPLL_OUTPUT_OUTPUT = 3U }
	FLL and PLL output mode. More...

enum	cy_en_pll_400M_ssgc_depth_t { CY_SYSCLK_SSCG_DEPTH_MINUS_0_5 = 0x029u , CY_SYSCLK_SSCG_DEPTH_MINUS_1_0 = 0x052u , CY_SYSCLK_SSCG_DEPTH_MINUS_2_0 = 0x0A4u , CY_SYSCLK_SSCG_DEPTH_MINUS_3_0 = 0x0F6u }
	SSCG modulation depth of PLL 400M spreading mode. More...

enum	cy_en_pll_400M_ssgc_rate_t { CY_SYSCLK_SSCG_RATE_DIV_4096 = 0u , CY_SYSCLK_SSCG_RATE_DIV_2048 = 1u , CY_SYSCLK_SSCG_RATE_DIV_1024 = 2u , CY_SYSCLK_SSCG_RATE_DIV_512 = 3u , CY_SYSCLK_SSCG_RATE_DIV_256 = 4u }
	SSCG modulation rate of PLL 400M spreading mode. More...

Enumeration Type Documentation

FLL and PLL output mode.

See registers CLK_FLL_CONFIG3 and CLK_PLL_CONFIG0, bits BYPASS_SEL.

Enumerator
CY_SYSCLK_FLLPLL_OUTPUT_AUTO	Output FLL/PLL input source when not locked, and FLL/PLL output when locked.
CY_SYSCLK_FLLPLL_OUTPUT_AUTO1	Same as AUTO.
CY_SYSCLK_FLLPLL_OUTPUT_INPUT	Output FLL/PLL input source regardless of lock status.
CY_SYSCLK_FLLPLL_OUTPUT_OUTPUT	Output FLL/PLL output regardless of lock status. This can be dangerous if used to clock clkHf, because FLL/PLL output may be unstable

SSCG modulation depth of PLL 400M spreading mode.

See registers SSCG_DEPTH bit of PLL400M_STRUCT_CONFIG3.

SSCG modulation rate of PLL 400M spreading mode.

See registers SSCG_RATE bit of PLL400M_STRUCT_CONFIG3.