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CAPSENSE™ Middleware Library 5.0
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CAPSENSE™ Middleware Library 5.0
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Declares the BIST structure with custom scan parameters.
Data Fields | |
| uint16_t | modClk |
| The ModClk divider for a custom scan. More... | |
| uint16_t | snsClk |
| The SnsClk divider for a custom scan. More... | |
| uint16_t | convNum |
| The number of conversions for a custom scan. More... | |
| cy_en_capsense_bist_io_state_t | customISC |
| The inactive state of sensors during the custom scan. | |
| uint8_t | reserved0 |
| Reserved field. | |
| uint8_t | vrefGain |
| The Vref gain for a custom scan. | |
| uint8_t | idacMod |
| Sets the code of the modulation IDAC for a custom scan. | |
| uint8_t | idacGainIndex |
| Index of IDAC gain in table cy_stc_capsense_idac_gain_table_t. | |
| uint8_t | fineInitTime |
| Number of dummy SnsClk periods at fine initialization for a custom scan. | |
| uint16_t cy_stc_capsense_bist_custom_parameters_t::modClk |
The ModClk divider for a custom scan.
The minimum value is 1 and the maximum depends on a divider type, but for a reliable CSD HW block operation, it is recommended to provide a modulation clock frequency in the range from 1 to 50 MHz
| uint16_t cy_stc_capsense_bist_custom_parameters_t::snsClk |
The SnsClk divider for a custom scan.
The minimum value is 4 and the maximum is 4095, but for a reliable CSD HW block operation, it is recommended to provide an sensor clock frequency in the range from 100 to 6000 kHz
| uint16_t cy_stc_capsense_bist_custom_parameters_t::convNum |
The number of conversions for a custom scan.
The maximum raw counts is equal (convNum * snsClkDivider - 1), that corresponds to (2^Resolution - 1) in older notations. The minimum value is 4 and the maximum is 65535, but as the maximum raw counts is 65535, the convNum value should be less than (65536 / snsClkDivider)