cy_stc_sysclk_csv_config_t Struct Reference

Description

The CSV configuration structure.

Data Fields
uint16_t	startupDelay
	Startup delay time -1 (in reference clock cycles), after enable or DeepSleep wakeup, from reference clock start to monitored clock start. More...
uint16_t	period
	Period time. More...
uint16_t	lowerLimit
	Cycle time lower limit. More...
uint16_t	upperLimit
	Cycle time upper limit. More...
bool	clkSwitchEn
	Enable the clock switching to IMO feature.
bool	triggerEn
	Enable the HW trigger when a clock switching to IMO occurs.
bool	interruptEn
	Enable the CY_SYSCLK_INTR_SW_IMO interrupt when a clock switching to IMO occurs.

Field Documentation

startupDelay

uint16_t cy_stc_sysclk_csv_config_t::startupDelay

Startup delay time -1 (in reference clock cycles), after enable or DeepSleep wakeup, from reference clock start to monitored clock start.

At a minimum (both clocks running): STARTUP >= (PERIOD +3) * FREQ_RATIO - UPPER, with FREQ_RATIO = (Reference frequency / Monitored frequency) On top of that the actual clock startup delay and the margin for accuracy of both clocks must be added.

Note

The startupDelay is applicable only when CSV is enabled before PLL and/or ECO has started. Otherwise, CSV starts monitoring immediately after enabling and regardless of the startupDelay setting.

period

uint16_t cy_stc_sysclk_csv_config_t::period

Period time.

Set the Period -1, in monitored clock cycles, before the next monitored clock event happens. PERIOD <= (UPPER+1) / FREQ_RATIO -1, with FREQ_RATIO = (Reference frequency / Monitored frequency) In case the clocks are asynchronous: PERIOD <= UPPER / FREQ_RATIO -1 Additionally margin must be added for accuracy of both clocks.

lowerLimit

uint16_t cy_stc_sysclk_csv_config_t::lowerLimit

Cycle time lower limit.

Set the lower limit -1, in reference clock cycles, before the next monitored clock event is allowed to happen. If a monitored clock event happens before this limit is reached a CSV error is detected. LOWER must be at least 1 less than UPPER. In case the clocks are asynchronous LOWER must be at least 3 less than UPPER.

upperLimit

uint16_t cy_stc_sysclk_csv_config_t::upperLimit

Cycle time upper limit.

Set the upper limit -1, in reference clock cycles, before (or same time) the next monitored clock event must happen. If a monitored clock event does not happen before this limit is reached, or does not happen at all (clock loss), a CSV error is detected.