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CAT2 Peripheral Driver Library
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CAT2 Peripheral Driver Library
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I2S initialization configuration.
Data Fields | |
| uint8_t | clkDiv |
| CLK_SEL divider: 1: Bypass, 2: 1/2, 3: 1/3, ..., 64: 1/64. More... | |
| bool | extClk |
| 'false': internal clock, 'true': external clock. More... | |
| cy_en_i2s_alignment_t | txAlignment |
| TX data alignment, see: cy_en_i2s_alignment_t. More... | |
| cy_en_i2s_ws_pw_t | txWsPulseWidth |
| TX Word Select pulse width. More... | |
| bool | txSckoInversion |
| TX SCKO polarity: 'false': Serial data is transmitted off the falling bit clock edge (accordingly to the I2S Standard); 'true': Serial data is transmitted off the rising bit clock edge. More... | |
| uint8_t | txChannels |
| The number of TX channels, the valid range is 1...8 for TDM modes. More... | |
| cy_en_i2s_len_t | txChannelLength |
| The TX channel length, see cy_en_i2s_len_t, the value of this parameter is ignored in TDM modes, the real channel length is 32 bit in these modes. More... | |
| cy_en_i2s_len_t | txWordLength |
| The TX word length, see cy_en_i2s_len_t, must be less or equal to txChannelLength. More... | |
| cy_en_i2s_overhead_t | txOverheadValue |
| The TX overhead bits value when the word length is less than the channel length. More... | |
| uint8_t | txFifoTriggerLevel |
| The TX FIFO interrupt trigger level (0, 1, ..., 255). More... | |
| uint8_t cy_stc_i2s_config_t::clkDiv |
CLK_SEL divider: 1: Bypass, 2: 1/2, 3: 1/3, ..., 64: 1/64.
| bool cy_stc_i2s_config_t::extClk |
'false': internal clock, 'true': external clock.
| cy_en_i2s_alignment_t cy_stc_i2s_config_t::txAlignment |
TX data alignment, see: cy_en_i2s_alignment_t.
| cy_en_i2s_ws_pw_t cy_stc_i2s_config_t::txWsPulseWidth |
TX Word Select pulse width.
The value of this parameter is ignored in I2S and the Left Justified modes WS pulse width is always "one channel length" in these modes.
| bool cy_stc_i2s_config_t::txSckoInversion |
TX SCKO polarity: 'false': Serial data is transmitted off the falling bit clock edge (accordingly to the I2S Standard); 'true': Serial data is transmitted off the rising bit clock edge.
Effective only in Master mode.
| uint8_t cy_stc_i2s_config_t::txChannels |
The number of TX channels, the valid range is 1...8 for TDM modes.
In the I2S and Left Justified modes, the value of this parameter is ignored - the real number of channels is always 2 in these modes.
| cy_en_i2s_len_t cy_stc_i2s_config_t::txChannelLength |
The TX channel length, see cy_en_i2s_len_t, the value of this parameter is ignored in TDM modes, the real channel length is 32 bit in these modes.
| cy_en_i2s_len_t cy_stc_i2s_config_t::txWordLength |
The TX word length, see cy_en_i2s_len_t, must be less or equal to txChannelLength.
| cy_en_i2s_overhead_t cy_stc_i2s_config_t::txOverheadValue |
The TX overhead bits value when the word length is less than the channel length.
| uint8_t cy_stc_i2s_config_t::txFifoTriggerLevel |
The TX FIFO interrupt trigger level (0, 1, ..., 255).
A trigger event is generated when the TX FIFO has less entries than the number in this field.