Macros to check current SPI transfer status returned by Cy_SCB_SPI_GetTransferStatus function. More...

Macros
#define	CY_SCB_SPI_TRANSFER_ACTIVE (0x01UL)
	Transfer operation started by Cy_SCB_SPI_Transfer is in progress.

#define	CY_SCB_SPI_TRANSFER_IN_FIFO (0x02UL)
	All data elements specified by Cy_SCB_SPI_Transfer for transmission have been loaded into the TX FIFO.

#define	CY_SCB_SPI_SLAVE_TRANSFER_ERR (SCB_INTR_S_SPI_BUS_ERROR_Msk)
	The slave was deselected at the wrong time. More...

#define	CY_SCB_SPI_TRANSFER_OVERFLOW (SCB_INTR_RX_OVERFLOW_Msk)
	RX FIFO was full and there was an attempt to write to it. More...

#define	CY_SCB_SPI_TRANSFER_UNDERFLOW (SCB_INTR_TX_UNDERFLOW_Msk)
	Applicable only for the slave mode. More...

#define	CY_SCB_SPI_TRANSFER_PARITY_ERR (SCB_INTR_RX_PARITY_ERROR_Msk)
	Parity error in received data frame. More...

Detailed Description

Macros to check current SPI transfer status returned by Cy_SCB_SPI_GetTransferStatus function.

Each SPI transfer status is encoded in a separate bit, therefore multiple bits may be set to indicate the current status.

Macro Definition Documentation

#define CY_SCB_SPI_SLAVE_TRANSFER_ERR (SCB_INTR_S_SPI_BUS_ERROR_Msk)

The slave was deselected at the wrong time.

#define CY_SCB_SPI_TRANSFER_OVERFLOW (SCB_INTR_RX_OVERFLOW_Msk)

RX FIFO was full and there was an attempt to write to it.

This additional data was dropped.

#define CY_SCB_SPI_TRANSFER_UNDERFLOW (SCB_INTR_TX_UNDERFLOW_Msk)

Applicable only for the slave mode.

The master tried to read more data elements than available in the TX FIFO.

Note: For the PSoC 4000S, PSoC 4100S, PSoC 4100S Plus, and PSoC 4500S series, the SPI in the Motorola mode generates the spare CY_SCB_TX_INTR_UNDERFLOW interrupt at the end of the transmission (the TX FIFO buffer is empty and no additional data is requested by the Master) in CY_SCB_SPI_CPHA0_CPOL0 and CY_SCB_SPI_CPHA1_CPOL0 SCLK modes. On the Slave side, the application can ignore the first interrupt. On the Master side, the packet checksum can be used on the application level to verify if the underflow interrupt is valid.

#define CY_SCB_SPI_TRANSFER_PARITY_ERR (SCB_INTR_RX_PARITY_ERROR_Msk)

Parity error in received data frame.