Enumerated Types

Enumerations
enum	cy_en_scb_spi_status_t {   CY_SCB_SPI_SUCCESS = 0U,   CY_SCB_SPI_BAD_PARAM = (CY_SCB_ID | CY_PDL_STATUS_ERROR | CY_SCB_SPI_ID | 1U),   CY_SCB_SPI_TRANSFER_BUSY = (CY_SCB_ID | CY_PDL_STATUS_ERROR | CY_SCB_SPI_ID | 2U) }
	SPI status codes. More...
enum	cy_en_scb_spi_mode_t {   CY_SCB_SPI_SLAVE,   CY_SCB_SPI_MASTER }
	SPI Modes. More...
enum	cy_en_scb_spi_sub_mode_t {   CY_SCB_SPI_MOTOROLA = 0x0U,   CY_SCB_SPI_TI_COINCIDES = 0x01U,   CY_SCB_SPI_NATIONAL = 0x02U,   CY_SCB_SPI_TI_PRECEDES = 0x05U }
	SPI Submodes. More...
enum	cy_en_scb_spi_sclk_mode_t {   CY_SCB_SPI_CPHA0_CPOL0 = 0U,   CY_SCB_SPI_CPHA1_CPOL0 = 1U,   CY_SCB_SPI_CPHA0_CPOL1 = 2U,   CY_SCB_SPI_CPHA1_CPOL1 = 3U }
	SPI SCLK Modes. More...
enum	cy_en_scb_spi_slave_select_t {   CY_SCB_SPI_SLAVE_SELECT0 = 0U,   CY_SCB_SPI_SLAVE_SELECT1 = 1U,   CY_SCB_SPI_SLAVE_SELECT2 = 2U,   CY_SCB_SPI_SLAVE_SELECT3 = 3U }
	SPI Slave Selects. More...
enum	cy_en_scb_spi_polarity_t {   CY_SCB_SPI_ACTIVE_LOW = 0U,   CY_SCB_SPI_ACTIVE_HIGH = 1U }
	SPI Polarity. More...
enum	cy_en_scb_spi_parity_t {   CY_SCB_SPI_PARITY_NONE = 0U,   CY_SCB_SPI_PARITY_EVEN = 2U,   CY_SCB_SPI_PARITY_ODD = 3U }
	SPI Parity. More...
enum	cy_en_scb_spi_ss_setup_delay_t {   CY_SCB_SPI_SS_SETUP_DELAY_0_75_CYCLES = 0U,   CY_SCB_SPI_SS_SETUP_DELAY_1_75_CYCLES = 1U }
	Setup delay, between select activation and SCLK clock edge to sample the first MISO bit. More...
enum	cy_en_scb_spi_ss_hold_delay_t {   CY_SCB_SPI_SS_HOLD_DELAY_0_75_CYCLES = 0U,   CY_SCB_SPI_SS_HOLD_DELAY_1_75_CYCLES = 1U }
	Hold delay, between SPI clock edge to sample the last MISO bit, and SELECT deactivation. More...
enum	cy_en_scb_spi_ss_interframe_delay_t {   CY_SCB_SPI_SS_INTERFRAME_DELAY_1_5_CYCLES = 0U,   CY_SCB_SPI_SS_INTERFRAME_DELAY_2_5_CYCLES = 1U }
	Inter-dataframe delay, between SELECT activation and SCLK clock edge to sample the first MISO bit. More...

Detailed Description

Enumeration Type Documentation

cy_en_scb_spi_status_t

enum cy_en_scb_spi_status_t

SPI status codes.

Enumerator
CY_SCB_SPI_SUCCESS	Operation completed successfully.
CY_SCB_SPI_BAD_PARAM	One or more of input parameters are invalid.
CY_SCB_SPI_TRANSFER_BUSY	SPI is busy processing a transfer.

cy_en_scb_spi_mode_t

enum cy_en_scb_spi_mode_t

SPI Modes.

Enumerator
CY_SCB_SPI_SLAVE	Configures SCB for SPI Slave operation.
CY_SCB_SPI_MASTER	Configures SCB for SPI Master operation.

cy_en_scb_spi_sub_mode_t

enum cy_en_scb_spi_sub_mode_t

SPI Submodes.

Enumerator
CY_SCB_SPI_MOTOROLA	Configures an SPI for a standard Motorola SPI operation.
CY_SCB_SPI_TI_COINCIDES	Configures the SPI for the TI SPI operation. In the TI mode, the slave select is a pulse. In this case, the pulse coincides with the first bit.
CY_SCB_SPI_NATIONAL	Configures an SPI for the National SPI operation. This is a half-duplex mode of operation.
CY_SCB_SPI_TI_PRECEDES	Configures an SPI for the TI SPI operation, in the TI mode. The slave select is a pulse. In this case the pulse precedes the first bit.

cy_en_scb_spi_sclk_mode_t

enum cy_en_scb_spi_sclk_mode_t

SPI SCLK Modes.

Enumerator
CY_SCB_SPI_CPHA0_CPOL0	Clock is active low, data is changed on first edge.
CY_SCB_SPI_CPHA1_CPOL0	Clock is active low, data is changed on second edge.
CY_SCB_SPI_CPHA0_CPOL1	Clock is active high, data is changed on first edge.
CY_SCB_SPI_CPHA1_CPOL1	Clock is active high, data is changed on second edge.

cy_en_scb_spi_slave_select_t

enum cy_en_scb_spi_slave_select_t

SPI Slave Selects.

Enumerator
CY_SCB_SPI_SLAVE_SELECT0	Master will use Slave Select 0.
CY_SCB_SPI_SLAVE_SELECT1	Master will use Slave Select 1.
CY_SCB_SPI_SLAVE_SELECT2	Master will use Slave Select 2.
CY_SCB_SPI_SLAVE_SELECT3	Master will use Slave Select 3.

cy_en_scb_spi_polarity_t

enum cy_en_scb_spi_polarity_t

SPI Polarity.

Enumerator
CY_SCB_SPI_ACTIVE_LOW	Signal in question is active low.
CY_SCB_SPI_ACTIVE_HIGH	Signal in question is active high.

cy_en_scb_spi_parity_t

enum cy_en_scb_spi_parity_t

SPI Parity.

Note

Only applicable for PSOC 4100S Max.

Enumerator
CY_SCB_SPI_PARITY_NONE	SPI has no parity check.
CY_SCB_SPI_PARITY_EVEN	SPI has even parity check.
CY_SCB_SPI_PARITY_ODD	SPI has odd parity check.

cy_en_scb_spi_ss_setup_delay_t

enum cy_en_scb_spi_ss_setup_delay_t

Setup delay, between select activation and SCLK clock edge to sample the first MISO bit.

Note

Only applicable for PSOC 4100S Max.

Enumerator
CY_SCB_SPI_SS_SETUP_DELAY_0_75_CYCLES	0.75 SPI clock cycles
CY_SCB_SPI_SS_SETUP_DELAY_1_75_CYCLES	1.75 SPI clock cycles

cy_en_scb_spi_ss_hold_delay_t

enum cy_en_scb_spi_ss_hold_delay_t

Hold delay, between SPI clock edge to sample the last MISO bit, and SELECT deactivation.

Note

Only applicable for PSOC 4100S Max.

Enumerator
CY_SCB_SPI_SS_HOLD_DELAY_0_75_CYCLES	0.75 SPI clock cycles
CY_SCB_SPI_SS_HOLD_DELAY_1_75_CYCLES	1.75 SPI clock cycles

cy_en_scb_spi_ss_interframe_delay_t

enum cy_en_scb_spi_ss_interframe_delay_t

Inter-dataframe delay, between SELECT activation and SCLK clock edge to sample the first MISO bit.

Note

Only applicable for PSOC 4100S Max.

Enumerator
CY_SCB_SPI_SS_INTERFRAME_DELAY_1_5_CYCLES	1.5 SPI clock cycles
CY_SCB_SPI_SS_INTERFRAME_DELAY_2_5_CYCLES	2.5 SPI clock cycles