|
#define | CY_MSCLP_REG_OFFSET_CTL (offsetof(MSCLP_Type, CTL)) |
| The register offset.
|
|
#define | CY_MSCLP_REG_OFFSET_SPARE (offsetof(MSCLP_Type, SPARE)) |
| The register offset.
|
|
#define | CY_MSCLP_REG_OFFSET_SCAN_CTL1 (offsetof(MSCLP_Type, SCAN_CTL1)) |
| The register offset.
|
|
#define | CY_MSCLP_REG_OFFSET_SCAN_CTL2 (offsetof(MSCLP_Type, SCAN_CTL2)) |
| The register offset.
|
|
#define | CY_MSCLP_REG_OFFSET_INIT_CTL1 (offsetof(MSCLP_Type, INIT_CTL1)) |
| The register offset.
|
|
#define | CY_MSCLP_REG_OFFSET_INIT_CTL2 (offsetof(MSCLP_Type, INIT_CTL2)) |
| The register offset.
|
|
#define | CY_MSCLP_REG_OFFSET_INIT_CTL3 (offsetof(MSCLP_Type, INIT_CTL3)) |
| The register offset.
|
|
#define | CY_MSCLP_REG_OFFSET_INIT_CTL4 (offsetof(MSCLP_Type, INIT_CTL4)) |
| The register offset.
|
|
#define | CY_MSCLP_REG_OFFSET_SENSE_DUTY_CTL (offsetof(MSCLP_Type, SENSE_DUTY_CTL)) |
| The register offset.
|
|
#define | CY_MSCLP_REG_OFFSET_SENSE_PERIOD_CTL (offsetof(MSCLP_Type, SENSE_PERIOD_CTL)) |
| The register offset.
|
|
#define | CY_MSCLP_REG_OFFSET_FILTER_CTL (offsetof(MSCLP_Type, FILTER_CTL)) |
| The register offset.
|
|
#define | CY_MSCLP_REG_OFFSET_CCOMP_CDAC_CTL (offsetof(MSCLP_Type, CCOMP_CDAC_CTL)) |
| The register offset.
|
|
#define | CY_MSCLP_REG_OFFSET_DITHER_CDAC_CTL (offsetof(MSCLP_Type, DITHER_CDAC_CTL)) |
| The register offset.
|
|
#define | CY_MSCLP_REG_OFFSET_MSCCMP_CTL (offsetof(MSCLP_Type, MSCCMP_CTL)) |
| The MSCCMP_CTL register offset.
|
|
#define | CY_MSCLP_REG_OFFSET_OBS_CTL (offsetof(MSCLP_Type, OBS_CTL)) |
| The OBS_CTL register offset.
|
|
#define | CY_MSCLP_REG_OFFSET_AOS_CTL (offsetof(MSCLP_Type, AOS_CTL)) |
| The AOS_CTL register offset.
|
|
#define | CY_MSCLP_REG_OFFSET_CE_CTL (offsetof(MSCLP_Type, CE_CTL)) |
| The CE_CTL register offset.
|
|
#define | CY_MSCLP_REG_OFFSET_PUMP_CTL (offsetof(MSCLP_Type, PUMP_CTL)) |
| The PUMP_CTL register offset.
|
|
#define | CY_MSCLP_REG_OFFSET_IMO_CTL (offsetof(MSCLP_Type, IMO_CTL)) |
| The IMO_CTL register offset.
|
|
#define | CY_MSCLP_REG_OFFSET_INTR (offsetof(MSCLP_Type, INTR)) |
| The register offset.
|
|
#define | CY_MSCLP_REG_OFFSET_INTR_SET (offsetof(MSCLP_Type, INTR_SET)) |
| The register offset.
|
|
#define | CY_MSCLP_REG_OFFSET_INTR_MASK (offsetof(MSCLP_Type, INTR_MASK)) |
| The register offset.
|
|
#define | CY_MSCLP_REG_OFFSET_INTR_MASKED (offsetof(MSCLP_Type, INTR_MASKED)) |
| The register offset.
|
|
#define | CY_MSCLP_REG_OFFSET_INTR_LP (offsetof(MSCLP_Type, INTR_LP)) |
| The register offset.
|
|
#define | CY_MSCLP_REG_OFFSET_INTR_LP_SET (offsetof(MSCLP_Type, INTR_LP_SET)) |
| The register offset.
|
|
#define | CY_MSCLP_REG_OFFSET_INTR_LP_MASK (offsetof(MSCLP_Type, INTR_LP_MASK)) |
| The register offset.
|
|
#define | CY_MSCLP_REG_OFFSET_INTR_LP_MASKED (offsetof(MSCLP_Type, INTR_LP_MASKED)) |
| The register offset.
|
|
#define | CY_MSCLP_REG_OFFSET_WAKEUP_CMD (offsetof(MSCLP_Type, WAKEUP_CMD)) |
| The WAKEUP_CMD register offset.
|
|
#define | CY_MSCLP_REG_OFFSET_MRSS_CMD (offsetof(MSCLP_Type, MRSS_CMD)) |
| The MRSS_CMD register offset.
|
|
#define | CY_MSCLP_REG_OFFSET_MRSS_STATUS (offsetof(MSCLP_Type, MRSS_STATUS)) |
| The MRSS_STATUS register offset.
|
|
#define | CY_MSCLP_REG_OFFSET_AOS_STATUS (offsetof(MSCLP_Type, AOS_STATUS)) |
| The AOS_STATUS register offset.
|
|
#define | CY_MSCLP_REG_OFFSET_SW_SEL_GPIO (offsetof(MSCLP_Type, SW_SEL_GPIO)) |
| The SW_SEL_GPIO register offset.
|
|
#define | CY_MSCLP_REG_OFFSET_SW_SEL_CDAC_RE (offsetof(MSCLP_Type, SW_SEL_CDAC_RE)) |
| The SW_SEL_CDAC_RE register offset.
|
|
#define | CY_MSCLP_REG_OFFSET_SW_SEL_CDAC_CO (offsetof(MSCLP_Type, SW_SEL_CDAC_CO)) |
| The SW_SEL_CDAC_CO register offset.
|
|
#define | CY_MSCLP_REG_OFFSET_SW_SEL_CDAC_CF (offsetof(MSCLP_Type, SW_SEL_CDAC_CF)) |
| The SW_SEL_CDAC_CF register offset.
|
|
#define | CY_MSCLP_REG_OFFSET_SW_SEL_BGR (offsetof(MSCLP_Type, SW_SEL_BGR)) |
| The SW_SEL_BGR register offset.
|
|
#define | CY_MSCLP_REG_OFFSET_SW_SEL_CSW_FUNC0 (offsetof(MSCLP_Type, SW_SEL_CSW_FUNC[0])) |
| The SW_SEL_CSW_FUNC[0] register offset.
|
|
#define | CY_MSCLP_REG_OFFSET_SW_SEL_CSW_FUNC1 (offsetof(MSCLP_Type, SW_SEL_CSW_FUNC[1])) |
| The SW_SEL_CSW_FUNC[1] register offset.
|
|
#define | CY_MSCLP_REG_OFFSET_SW_SEL_CSW_FUNC2 (offsetof(MSCLP_Type, SW_SEL_CSW_FUNC[2])) |
| The SW_SEL_CSW_FUNC[2] register offset.
|
|
#define | CY_MSCLP_REG_OFFSET_SW_SEL_CSW_FUNC3 (offsetof(MSCLP_Type, SW_SEL_CSW_FUNC[3])) |
| The SW_SEL_CSW_FUNC[3] register offset.
|
|
#define | CY_MSCLP_REG_OFFSET_SW_SEL_CSW_FUNC4 (offsetof(MSCLP_Type, SW_SEL_CSW_FUNC[4])) |
| The SW_SEL_CSW_FUNC[4] register offset.
|
|
#define | CY_MSCLP_REG_OFFSET_SW_SEL_CSW_FUNC5 (offsetof(MSCLP_Type, SW_SEL_CSW_FUNC[5])) |
| The SW_SEL_CSW_FUNC[5] register offset.
|
|
#define | CY_MSCLP_REG_OFFSET_SW_SEL_CSW_FUNC6 (offsetof(MSCLP_Type, SW_SEL_CSW_FUNC[6])) |
| The SW_SEL_CSW_FUNC[6] register offset.
|
|
#define | CY_MSCLP_REG_OFFSET_SW_SEL_CSW_FUNC7 (offsetof(MSCLP_Type, SW_SEL_CSW_FUNC[7])) |
| The SW_SEL_CSW_FUNC[7] register offset.
|
|
#define | CY_MSCLP_REG_OFFSET_CSW_CTL_LO (offsetof(MSCLP_Type, CSW_CTL_LO)) |
| The CSW_CTL_LO register offset.
|
|
#define | CY_MSCLP_REG_OFFSET_MODE0_SENSE_DUTY_CTL (offsetof(MSCLP_Type, MODE[0].SENSE_DUTY_CTL)) |
| The register offset.
|
|
#define | CY_MSCLP_REG_OFFSET_MODE0_SW_SEL_CDAC_FL (offsetof(MSCLP_Type, MODE[0].SW_SEL_CDAC_FL)) |
| The register offset.
|
|
#define | CY_MSCLP_REG_OFFSET_MODE0_SW_SEL_TOP (offsetof(MSCLP_Type, MODE[0].SW_SEL_TOP)) |
| The register offset.
|
|
#define | CY_MSCLP_REG_OFFSET_MODE0_SW_SEL_COMP (offsetof(MSCLP_Type, MODE[0].SW_SEL_COMP)) |
| The register offset.
|
|
#define | CY_MSCLP_REG_OFFSET_MODE0_SW_SEL_SH (offsetof(MSCLP_Type, MODE[0].SW_SEL_SH)) |
| The register offset.
|
|
#define | CY_MSCLP_REG_OFFSET_MODE0_SW_SEL_CMOD1 (offsetof(MSCLP_Type, MODE[0].SW_SEL_CMOD1)) |
| The MODE[0].SW_SEL_CMOD1 register offset.
|
|
#define | CY_MSCLP_REG_OFFSET_MODE0_SW_SEL_CMOD2 (offsetof(MSCLP_Type, MODE[0].SW_SEL_CMOD2)) |
| The MODE[0].SW_SEL_CMOD2 register offset.
|
|
#define | CY_MSCLP_REG_OFFSET_MODE0_SW_SEL_CMOD3 (offsetof(MSCLP_Type, MODE[0].SW_SEL_CMOD3)) |
| The MODE[0].SW_SEL_CMOD3 register offset.
|
|
#define | CY_MSCLP_REG_OFFSET_MODE0_SW_SEL_CMOD4 (offsetof(MSCLP_Type, MODE[0].SW_SEL_CMOD4)) |
| The MODE[0].SW_SEL_CMOD4 register offset.
|
|
#define | CY_MSCLP_REG_OFFSET_MODE1_SENSE_DUTY_CTL (offsetof(MSCLP_Type, MODE[1].SENSE_DUTY_CTL)) |
| The register offset.
|
|
#define | CY_MSCLP_REG_OFFSET_MODE1_SW_SEL_CDAC_FL (offsetof(MSCLP_Type, MODE[1].SW_SEL_CDAC_FL)) |
| The register offset.
|
|
#define | CY_MSCLP_REG_OFFSET_MODE1_SW_SEL_TOP (offsetof(MSCLP_Type, MODE[1].SW_SEL_TOP)) |
| The register offset.
|
|
#define | CY_MSCLP_REG_OFFSET_MODE1_SW_SEL_COMP (offsetof(MSCLP_Type, MODE[1].SW_SEL_COMP)) |
| The register offset.
|
|
#define | CY_MSCLP_REG_OFFSET_MODE1_SW_SEL_SH (offsetof(MSCLP_Type, MODE[1].SW_SEL_SH)) |
| The register offset.
|
|
#define | CY_MSCLP_REG_OFFSET_MODE1_SW_SEL_CMOD1 (offsetof(MSCLP_Type, MODE[1].SW_SEL_CMOD1)) |
| The MODE[1].SW_SEL_CMOD1 register offset.
|
|
#define | CY_MSCLP_REG_OFFSET_MODE1_SW_SEL_CMOD2 (offsetof(MSCLP_Type, MODE[1].SW_SEL_CMOD2)) |
| The MODE[1].SW_SEL_CMOD2 register offset.
|
|
#define | CY_MSCLP_REG_OFFSET_MODE1_SW_SEL_CMOD3 (offsetof(MSCLP_Type, MODE[1].SW_SEL_CMOD3)) |
| The MODE[1].SW_SEL_CMOD3 register offset.
|
|
#define | CY_MSCLP_REG_OFFSET_MODE1_SW_SEL_CMOD4 (offsetof(MSCLP_Type, MODE[1].SW_SEL_CMOD4)) |
| The MODE[1].SW_SEL_CMOD4 register offset.
|
|
#define | CY_MSCLP_REG_OFFSET_MODE2_SENSE_DUTY_CTL (offsetof(MSCLP_Type, MODE[2].SENSE_DUTY_CTL)) |
| The register offset.
|
|
#define | CY_MSCLP_REG_OFFSET_MODE2_SW_SEL_CDAC_FL (offsetof(MSCLP_Type, MODE[2].SW_SEL_CDAC_FL)) |
| The register offset.
|
|
#define | CY_MSCLP_REG_OFFSET_MODE2_SW_SEL_TOP (offsetof(MSCLP_Type, MODE[2].SW_SEL_TOP)) |
| The register offset.
|
|
#define | CY_MSCLP_REG_OFFSET_MODE2_SW_SEL_COMP (offsetof(MSCLP_Type, MODE[2].SW_SEL_COMP)) |
| The register offset.
|
|
#define | CY_MSCLP_REG_OFFSET_MODE2_SW_SEL_SH (offsetof(MSCLP_Type, MODE[2].SW_SEL_SH)) |
| The register offset.
|
|
#define | CY_MSCLP_REG_OFFSET_MODE2_SW_SEL_CMOD1 (offsetof(MSCLP_Type, MODE[2].SW_SEL_CMOD1)) |
| The MODE[2].SW_SEL_CMOD1 register offset.
|
|
#define | CY_MSCLP_REG_OFFSET_MODE2_SW_SEL_CMOD2 (offsetof(MSCLP_Type, MODE[2].SW_SEL_CMOD2)) |
| The MODE[2].SW_SEL_CMOD2 register offset.
|
|
#define | CY_MSCLP_REG_OFFSET_MODE2_SW_SEL_CMOD3 (offsetof(MSCLP_Type, MODE[2].SW_SEL_CMOD3)) |
| The MODE[2].SW_SEL_CMOD3 register offset.
|
|
#define | CY_MSCLP_REG_OFFSET_MODE2_SW_SEL_CMOD4 (offsetof(MSCLP_Type, MODE[2].SW_SEL_CMOD4)) |
| The MODE[2].SW_SEL_CMOD4 register offset.
|
|
#define | CY_MSCLP_REG_OFFSET_MODE3_SENSE_DUTY_CTL (offsetof(MSCLP_Type, MODE[3].SENSE_DUTY_CTL)) |
| The register offset.
|
|
#define | CY_MSCLP_REG_OFFSET_MODE3_SW_SEL_CDAC_FL (offsetof(MSCLP_Type, MODE[3].SW_SEL_CDAC_FL)) |
| The register offset.
|
|
#define | CY_MSCLP_REG_OFFSET_MODE3_SW_SEL_TOP (offsetof(MSCLP_Type, MODE[3].SW_SEL_TOP)) |
| The register offset.
|
|
#define | CY_MSCLP_REG_OFFSET_MODE3_SW_SEL_COMP (offsetof(MSCLP_Type, MODE[3].SW_SEL_COMP)) |
| The register offset.
|
|
#define | CY_MSCLP_REG_OFFSET_MODE3_SW_SEL_SH (offsetof(MSCLP_Type, MODE[3].SW_SEL_SH)) |
| The register offset.
|
|
#define | CY_MSCLP_REG_OFFSET_MODE3_SW_SEL_CMOD1 (offsetof(MSCLP_Type, MODE[3].SW_SEL_CMOD1)) |
| The MODE[3].SW_SEL_CMOD1 register offset.
|
|
#define | CY_MSCLP_REG_OFFSET_MODE3_SW_SEL_CMOD2 (offsetof(MSCLP_Type, MODE[3].SW_SEL_CMOD2)) |
| The MODE[3].SW_SEL_CMOD2 register offset.
|
|
#define | CY_MSCLP_REG_OFFSET_MODE3_SW_SEL_CMOD3 (offsetof(MSCLP_Type, MODE[3].SW_SEL_CMOD3)) |
| The MODE[3].SW_SEL_CMOD3 register offset.
|
|
#define | CY_MSCLP_REG_OFFSET_MODE3_SW_SEL_CMOD4 (offsetof(MSCLP_Type, MODE[3].SW_SEL_CMOD4)) |
| The MODE[3].SW_SEL_CMOD4 register offset.
|
|
#define | CY_MSCLP_REG_OFFSET_SENSOR_DATA (offsetof(MSCLP_Type, SENSOR_DATA)) |
| The SENSOR_DATA memory array offset.
|
|
#define | CY_MSCLP_REG_OFFSET_SNS_LP_AOS_SNS_CTL0 (offsetof(MSCLP_Type, SNS.SNS_LP_AOS_SNS_CTL0)) |
| The SNS_LP_AOS_SNS_CTL0 register offset.
|
|
#define | CY_MSCLP_REG_OFFSET_SNS_LP_AOS_SNS_CTL1 (offsetof(MSCLP_Type, SNS.SNS_LP_AOS_SNS_CTL1)) |
| The SNS_LP_AOS_SNS_CTL1 register offset.
|
|
#define | CY_MSCLP_REG_OFFSET_SNS_LP_AOS_SNS_CTL2 (offsetof(MSCLP_Type, SNS.SNS_LP_AOS_SNS_CTL2)) |
| The SNS_LP_AOS_SNS_CTL2 register offset.
|
|
#define | CY_MSCLP_REG_OFFSET_SNS_LP_AOS_SNS_CTL3 (offsetof(MSCLP_Type, SNS.SNS_LP_AOS_SNS_CTL3)) |
| The SNS_LP_AOS_SNS_CTL3 register offset.
|
|
#define | CY_MSCLP_REG_OFFSET_SNS_LP_AOS_SNS_CTL4 (offsetof(MSCLP_Type, SNS.SNS_LP_AOS_SNS_CTL4)) |
| The SNS_LP_AOS_SNS_CTL4 register offset.
|
|
#define | CY_MSCLP_REG_OFFSET_SNS_SW_SEL_CSW_HI_MASK2 (offsetof(MSCLP_Type, SNS.SNS_SW_SEL_CSW_HI_MASK2)) |
| The SNS_SW_SEL_CSW_HI_MASK2 register offset.
|
|
#define | CY_MSCLP_REG_OFFSET_SNS_SW_SEL_CSW_HI_MASK1 (offsetof(MSCLP_Type, SNS.SNS_SW_SEL_CSW_HI_MASK1)) |
| The SNS_SW_SEL_CSW_HI_MASK1 register offset.
|
|
#define | CY_MSCLP_REG_OFFSET_SNS_SW_SEL_CSW_HI_MASK0 (offsetof(MSCLP_Type, SNS.SNS_SW_SEL_CSW_HI_MASK0)) |
| The SNS_SW_SEL_CSW_HI_MASK0 register offset.
|
|
#define | CY_MSCLP_REG_OFFSET_SNS_SW_SEL_CSW_LO_MASK2 (offsetof(MSCLP_Type, SNS.SNS_SW_SEL_CSW_LO_MASK2)) |
| The SNS_SW_SEL_CSW_LO_MASK2 register offset.
|
|
#define | CY_MSCLP_REG_OFFSET_SNS_SW_SEL_CSW_LO_MASK1 (offsetof(MSCLP_Type, SNS.SNS_SW_SEL_CSW_LO_MASK1)) |
| The SNS_SW_SEL_CSW_LO_MASK1 register offset.
|
|
#define | CY_MSCLP_REG_OFFSET_SNS_SW_SEL_CSW_LO_MASK0 (offsetof(MSCLP_Type, SNS.SNS_SW_SEL_CSW_LO_MASK0)) |
| The SNS_SW_SEL_CSW_LO_MASK0 register offset.
|
|
#define | CY_MSCLP_REG_OFFSET_SNS_SCAN_CTL (offsetof(MSCLP_Type, SNS.SNS_SCAN_CTL)) |
| The SNS_SCAN_CTL register offset.
|
|
#define | CY_MSCLP_REG_OFFSET_SNS_CDAC_CTL (offsetof(MSCLP_Type, SNS.SNS_CDAC_CTL)) |
| The SNS_CDAC_CTL register offset.
|
|
#define | CY_MSCLP_REG_OFFSET_SNS_CTL (offsetof(MSCLP_Type, SNS.SNS_CTL)) |
| The SNS_CTL register offset.
|
|
#define | CY_MSCLP_REG_OFFSET_RESULT_FIFO_RD (offsetof(MSCLP_Type, SNS.RESULT_FIFO_RD)) |
| The RESULT_FIFO_RD register offset.
|
|
#define | CY_MSCLP_REG_OFFSET_STATUS1 (offsetof(MSCLP_Type, SNS.STATUS1)) |
| The STATUS1 register offset.
|
|
#define | CY_MSCLP_REG_OFFSET_STATUS2 (offsetof(MSCLP_Type, SNS.STATUS2)) |
| The STATUS2 register offset.
|
|
#define | CY_MSCLP_REG_OFFSET_STATUS3 (offsetof(MSCLP_Type, SNS.STATUS3)) |
| The STATUS3 register offset.
|
|
#define | CY_MSCLP_REG_OFFSET_RESULT_FIFO_STATUS (offsetof(MSCLP_Type, SNS.RESULT_FIFO_STATUS)) |
| The RESULT_FIFO_STATUS register offset.
|
|
#define | CY_MSCLP_REG_OFFSET_RESULT_FIFO_STATUS2 (offsetof(MSCLP_Type, SNS.RESULT_FIFO_STATUS2)) |
| The RESULT_FIFO_STATUS2 register offset.
|
|
#define | CY_MSCLP_REG_OFFSET_CE_STATUS (offsetof(MSCLP_Type, SNS.CE_STATUS)) |
| The CE_STATUS register offset.
|
|
#define | CY_MSCLP_REG_OFFSET_BRIDGE_STATUS (offsetof(MSCLP_Type, SNS.BRIDGE_STATUS)) |
| The BRIDGE_STATUS register offset.
|
|
#define | CY_MSCLP_REG_OFFSET_FRAME_CMD (offsetof(MSCLP_Type, SNS.FRAME_CMD)) |
| The FRAME_CMD register offset.
|
|
#define | CY_MSCLP_REG_OFFSET_CE_CMD (offsetof(MSCLP_Type, SNS.CE_CMD)) |
| The CE_CMD register offset.
|
|
#define | CY_MSCLP_REG_OFFSET_FIFO_CMD (offsetof(MSCLP_Type, SNS.FIFO_CMD)) |
| The FIFO_CMD register offset.
|
|
#define | CY_MSCLP_REG_OFFSET_CE_INIT_CTL (offsetof(MSCLP_Type, SNS.CE_INIT_CTL)) |
| The CE_INIT_CTL register offset.
|
|
#define | CY_MSCLP_REG_OFFSET_TRIM_CTL (offsetof(MSCLP_Type, TRIM_CTL)) |
| The TRIM_CTL register offset.
|
|
#define | CY_MSCLP_REG_OFFSET_CLK_IMO_TRIM1 (offsetof(MSCLP_Type, CLK_IMO_TRIM1)) |
| The CLK_IMO_TRIM1 register offset.
|
|
#define | CY_MSCLP_REG_OFFSET_CLK_IMO_TRIM2 (offsetof(MSCLP_Type, CLK_IMO_TRIM2)) |
| The CLK_IMO_TRIM2 register offset.
|
|
#define | CY_MSCLP_REG_OFFSET_CLK_IMO_TRIM3 (offsetof(MSCLP_Type, CLK_IMO_TRIM3)) |
| The CLK_IMO_TRIM3 register offset.
|
|
#define | CY_MSCLP_REG_OFFSET_PWR_BG_TRIM1 (offsetof(MSCLP_Type, PWR_BG_TRIM1)) |
| The PWR_BG_TRIM1 register offset.
|
|
#define | CY_MSCLP_REG_OFFSET_PWR_BG_TRIM2 (offsetof(MSCLP_Type, PWR_BG_TRIM2)) |
| The PWR_BG_TRIM2 register offset.
|
|
#define | CY_MSCLP_REG_OFFSET_PWR_BG_TRIM3 (offsetof(MSCLP_Type, PWR_BG_TRIM3)) |
| The PWR_BG_TRIM3 register offset.
|
|
#define | CY_MSCLP_REG_OFFSET_SW_SEL_CSW(index) (offsetof(MSCLP_Type, SW_SEL_CSW[(index)])) |
| The SW_SEL_CSW[x] register offset.
|
|
#define | CY_MSCLP_REG_OFFSET_SW_SEL_CSW_FUNC(index) (offsetof(MSCLP_Type, SW_SEL_CSW_FUNC[(index)])) |
| The SW_SEL_CSW_FUNC[x] register offset.
|
|
#define | CY_MSCLP_REG_OFFSET_MODE_SENSE_DUTY_CTL(index) (offsetof(MSCLP_Type, MODE[(index)].SENSE_DUTY_CTL)) |
| The MODE[x].SENSE_DUTY_CTL register offset.
|
|
#define | CY_MSCLP_REG_OFFSET_MODE_SW_SEL_CDAC_FL(index) (offsetof(MSCLP_Type, MODE[(index)].SW_SEL_CDAC_FL)) |
| The MODE[x].SW_SEL_CDAC_FL register offset.
|
|
#define | CY_MSCLP_REG_OFFSET_MODE_SW_SEL_TOP(index) (offsetof(MSCLP_Type, MODE[(index)].SW_SEL_TOP)) |
| The MODE[x].SW_SEL_TOP register offset.
|
|
#define | CY_MSCLP_REG_OFFSET_MODE_SW_SEL_COMP(index) (offsetof(MSCLP_Type, MODE[(index)].SW_SEL_COMP)) |
| The MODE[x].SW_SEL_COMP register offset.
|
|
#define | CY_MSCLP_REG_OFFSET_MODE_SW_SEL_SH(index) (offsetof(MSCLP_Type, MODE[(index)].SW_SEL_SH)) |
| The MODE[x].SW_SEL_SH register offset.
|
|
#define | CY_MSCLP_REG_OFFSET_MODE_SW_SEL_CMOD1(index) (offsetof(MSCLP_Type, MODE[(index)].SW_SEL_CMOD1)) |
| The MODE[x].SW_SEL_CMOD1 register offset.
|
|
#define | CY_MSCLP_REG_OFFSET_MODE_SW_SEL_CMOD2(index) (offsetof(MSCLP_Type, MODE[(index)].SW_SEL_CMOD2)) |
| The MODE[x].SW_SEL_CMOD2 register offset.
|
|
#define | CY_MSCLP_REG_OFFSET_MODE_SW_SEL_CMOD3(index) (offsetof(MSCLP_Type, MODE[(index)].SW_SEL_CMOD3)) |
| The MODE[x].SW_SEL_CMOD3 register offset.
|
|
#define | CY_MSCLP_REG_OFFSET_MODE_SW_SEL_CMOD4(index) (offsetof(MSCLP_Type, MODE[(index)].SW_SEL_CMOD4)) |
| The MODE[x].SW_SEL_CMOD4 register offset.
|
|