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CAT2 Peripheral Driver Library
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CAT2 Peripheral Driver Library
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Modules | |
| Registers Constants | |
Macros | |
| #define | CY_MSCLP_DRV_VERSION_MAJOR (2) |
| Driver major version. | |
| #define | CY_MSCLP_DRV_VERSION_MINOR (0) |
| Driver minor version. | |
| #define | CY_MSCLP_DRV_VERSION (100) |
| Macro to support the backward compatibility. More... | |
| #define | CY_MSCLP_ID (CY_PDL_DRV_ID(0x49u)) |
| MSCLP driver identifier. | |
| #define | CY_MSCLP_CONTEXT_INIT_VALUE {.lockKey = CY_MSCLP_NONE_KEY} |
| Initialization macro for the driver context variable. | |
| #define | CY_MSCLP_IMO_25_MHZ (0u) |
| MRSS IMO frequencies, to be used for cy_stc_msclp_mrss_config_t::imoFreq. More... | |
| #define | CY_MSCLP_IMO_38_MHZ (3u) |
| IMO frequency 38 MHz. | |
| #define | CY_MSCLP_IMO_46_MHZ (6u) |
| IMO frequency 46 MHz. | |
| #define | CY_MSCLP_SYNC_DIV_1 (0u) |
| MRSS IMO_CTL.CLOCK_SYNC_DIV values, to be used for cy_stc_msclp_mrss_config_t::syncDiv. More... | |
| #define | CY_MSCLP_SYNC_DIV_2 (1u) |
| Dividing by 2. | |
| #define | CY_MSCLP_SYNC_DIV_3 (2u) |
| Dividing by 3. | |
| #define | CY_MSCLP_SYNC_DIV_4 (3u) |
| Dividing by 4. | |
| #define | CY_MSCLP_SYNC_DIV_5 (4u) |
| Dividing by 5. | |
| #define | CY_MSCLP_SYNC_DIV_6 (5u) |
| Dividing by 6. | |
| #define | CY_MSCLP_SYNC_DIV_7 (6u) |
| Dividing by 7. | |
| #define | CY_MSCLP_SYNC_DIV_8 (7u) |
| Dividing by 8. | |
| #define | CY_MSCLP_PERCENTAGE_100 (100u) |
| One hundred percentage. | |
| #define | CY_MSCLP_8_BIT_SHIFT (8u) |
| 8-bit shift | |
| #define | CY_MSCLP_LSB_MASK (0x000000FFu) |
| The lowest 8-bit mask. | |
| #define | CY_MSCLP_11_SNS_REGS (11u) |
| Maximum number of registers in sensor frame with support of HW baselining (HW channel engine) | |
| #define | CY_MSCLP_6_SNS_REGS (6u) |
| Maximum number of registers in sensor frame with support up to 8 pin states. | |
| #define | CY_MSCLP_5_SNS_REGS (5u) |
| Maximum number of registers in sensor frame with support up to 4 pin states. | |
| #define | CY_MSCLP_SNS_SRAM_WORD_SIZE (MSCLP_SRAM_SIZE / 4U) |
| SNS.SENSOR_DATA size in 4-byte words. | |
| #define | CY_MSCLP_SENSOR_DATA_PTR(base) ((base)->SNS.SENSOR_DATA) |
| Pointer to the SNS.SENSOR_DATA[CY_MSCLP_SNS_SRAM_WORD_SIZE] internal SRAM. | |
| #define | CY_MSCLP_VDDA_PUMP_TRESHOLD (4000u) |
| VDDA threshold voltage in millivolts for PUMP enabling. | |
| #define | CY_MSCLP_CLK_LF_PERIOD_MAX (63u) |
| The maximum possible value of the CLK_LF period in microseconds. | |
| #define | CY_MSCLP_MRSS_TIMEOUT_FULL (7u) |
| Full (REF, IMO, PUMP) MRSS start timeout in CLK_LF periods. | |
| #define | CY_MSCLP_MRSS_TIMEOUT_SMALL (5u) |
| MRSS start timeout without PUMP (REF and IMO only) in CLK_LF periods. | |
| #define | CY_MSCLP_CSW_GLOBAL_FUNC_NR_MAX (8u) |
| The maximum possible pin function registers in the MSCLP IP block. | |
| #define | CY_MSCLP_SENSE_MODE_NR_MAX (4u) |
| The maximum possible sensing mode registers in the MSCLP IP block. | |
| #define | CY_MSCLP_MSC_DIV_MAX (1024u) |
| The maximal possible value of the cy_stc_msclp_mrss_config_t::mscDiv. | |
| #define CY_MSCLP_DRV_VERSION (100) |
Macro to support the backward compatibility.
Do not use for new designs.
| #define CY_MSCLP_IMO_25_MHZ (0u) |
MRSS IMO frequencies, to be used for cy_stc_msclp_mrss_config_t::imoFreq.
IMO frequency 25 MHz
| #define CY_MSCLP_SYNC_DIV_1 (0u) |
MRSS IMO_CTL.CLOCK_SYNC_DIV values, to be used for cy_stc_msclp_mrss_config_t::syncDiv.
Dividing by 1