CAT2 Peripheral Driver Library

General Description

Functions

void Cy_GPIO_SetAmuxSplit (cy_en_amux_split_t switchCtrl, cy_en_gpio_amuxconnect_t amuxConnect, cy_en_gpio_amuxselect_t amuxBus)
 Configure a specific AMux bus splitter switch cell into a specific configuration. More...
 
cy_en_gpio_amuxconnect_t Cy_GPIO_GetAmuxSplit (cy_en_amux_split_t switchCtrl, cy_en_gpio_amuxselect_t amuxBus)
 Returns the configuration of a specific AMux bus splitter switch cell. More...
 
__STATIC_INLINE uint32_t Cy_GPIO_Read (const GPIO_PRT_Type *base, uint32_t pinNum)
 Reads the current logic level on the input buffer of the pin. More...
 
__STATIC_INLINE void Cy_GPIO_Write (GPIO_PRT_Type *base, uint32_t pinNum, uint32_t value)
 Write a logic 0 or logic 1 state to the output driver. More...
 
__STATIC_INLINE uint32_t Cy_GPIO_ReadOut (const GPIO_PRT_Type *base, uint32_t pinNum)
 Reads the current logic level on the pin output driver. More...
 
__STATIC_INLINE void Cy_GPIO_Set (GPIO_PRT_Type *base, uint32_t pinNum)
 Set a pin output to logic state high. More...
 
__STATIC_INLINE void Cy_GPIO_Clr (GPIO_PRT_Type *base, uint32_t pinNum)
 Set a pin output to logic state Low. More...
 
__STATIC_INLINE void Cy_GPIO_Inv (GPIO_PRT_Type *base, uint32_t pinNum)
 Set a pin output logic state to the inverse of the current output logic state. More...
 
__STATIC_INLINE void Cy_GPIO_SetDrivemode (GPIO_PRT_Type *base, uint32_t pinNum, uint32_t value)
 Configures the pin output buffer drive mode and input buffer enable. More...
 
__STATIC_INLINE uint32_t Cy_GPIO_GetDrivemode (const GPIO_PRT_Type *base, uint32_t pinNum)
 Returns the pin output buffer drive mode and input buffer enable state. More...
 
__STATIC_INLINE void Cy_GPIO_SetVtrip (GPIO_PRT_Type *base, uint32_t value)
 Configures the GPIO port input buffer voltage Threshold mode. More...
 
__STATIC_INLINE uint32_t Cy_GPIO_GetVtrip (const GPIO_PRT_Type *base)
 Returns the port input buffer voltage Threshold mode. More...
 
__STATIC_INLINE void Cy_GPIO_SetSlewRate (GPIO_PRT_Type *base, uint32_t value)
 Configures the port output buffer slew rate. More...
 
__STATIC_INLINE uint32_t Cy_GPIO_GetSlewRate (const GPIO_PRT_Type *base)
 Returns the port output buffer slew rate. More...
 
__STATIC_INLINE void Cy_GPIO_MscControlEnable (const GPIO_PRT_Type *base, uint32_t pinNum)
 Enables control of the IO port analog signaling by the MSCV3LP IP block. More...
 
__STATIC_INLINE void Cy_GPIO_MscControlDisable (const GPIO_PRT_Type *base, uint32_t pinNum)
 Disables control of the IO port analog signaling by the MSCV3LP IP block. More...
 
__STATIC_INLINE bool Cy_GPIO_MscControlIsEnabled (const GPIO_PRT_Type *base, uint32_t pinNum)
 Returns the enable status of by the MSCV3LP IP block control for that particular pin. More...
 

Function Documentation

◆ Cy_GPIO_SetAmuxSplit()

void Cy_GPIO_SetAmuxSplit ( cy_en_amux_split_t  switchCtrl,
cy_en_gpio_amuxconnect_t  amuxConnect,
cy_en_gpio_amuxselect_t  amuxBus 
)

Configure a specific AMux bus splitter switch cell into a specific configuration.

Parameters
switchCtrlSelects specific AMux bus splitter cell between two segments. The cy_en_amux_split_t enumeration can be found in the GPIO header file for the device package.
amuxConnectSelects configuration of the three switches within the splitter cell
amuxBusSelects which AMux bus within the splitter is being configured

◆ Cy_GPIO_GetAmuxSplit()

cy_en_gpio_amuxconnect_t Cy_GPIO_GetAmuxSplit ( cy_en_amux_split_t  switchCtrl,
cy_en_gpio_amuxselect_t  amuxBus 
)

Returns the configuration of a specific AMux bus splitter switch cell.

Parameters
switchCtrlSelects specific AMux bus splitter cell between two segments. The cy_en_amux_split_t enumeration can be found in the GPIO header file for the device package.
amuxBusSelects which AMux bus within the splitter is being configured
Returns
Returns configuration of the three switches in the selected splitter cell

◆ Cy_GPIO_Read()

__STATIC_INLINE uint32_t Cy_GPIO_Read ( const GPIO_PRT_Type base,
uint32_t  pinNum 
)

Reads the current logic level on the input buffer of the pin.

Parameters
basePointer to the pin's port register base address
pinNumPosition of the pin bit-field within the port register. Bit position 8 is the routed pin through the port glitch filter.
Returns
Logic level present on the pin
Function Usage
/* Scenario: P0.3 was initialized and input buffer enabled */
/* Read the input state of P0.3 */
if(1UL == Cy_GPIO_Read(P0_0_PORT, P0_0_NUM))
{
/* Insert logic for High pin state */
}
else
{
/* Insert logic for Low pin state */
}

◆ Cy_GPIO_Write()

__STATIC_INLINE void Cy_GPIO_Write ( GPIO_PRT_Type base,
uint32_t  pinNum,
uint32_t  value 
)

Write a logic 0 or logic 1 state to the output driver.

This function should be used only for software driven pins. It does not have any effect on peripheral driven pins.

Parameters
basePointer to the pin's port register base address
pinNumPosition of the pin bit-field within the port register
valueLogic level to drive out on the pin
Function Usage
uint32_t pinState = 0UL;
/* Control P0.3 based on the pinState variable */
Cy_GPIO_Write(P0_0_PORT, P0_0_NUM, pinState);

◆ Cy_GPIO_ReadOut()

__STATIC_INLINE uint32_t Cy_GPIO_ReadOut ( const GPIO_PRT_Type base,
uint32_t  pinNum 
)

Reads the current logic level on the pin output driver.

Parameters
basePointer to the pin's port register base address
pinNumPosition of the pin bit-field within the port register
Returns
Logic level on the pin output driver
Function Usage
/* Write logic low to P0.3 */
Cy_GPIO_Write(P0_0_PORT, P0_0_NUM, 0UL);
/* Get the output value of P0.3 */
if(0UL != Cy_GPIO_ReadOut(P0_0_PORT, P0_0_NUM))
{
/* Insert error handling */
}

◆ Cy_GPIO_Set()

__STATIC_INLINE void Cy_GPIO_Set ( GPIO_PRT_Type base,
uint32_t  pinNum 
)

Set a pin output to logic state high.

This function should be used only for software driven pins. It does not have any effect on peripheral driven pins.

Parameters
basePointer to the pin's port register base address
pinNumPosition of the pin bit-field within the port register
Function Usage
/* Set P0.3 (out value = High) */
Cy_GPIO_Set(P0_0_PORT, P0_0_NUM);

◆ Cy_GPIO_Clr()

__STATIC_INLINE void Cy_GPIO_Clr ( GPIO_PRT_Type base,
uint32_t  pinNum 
)

Set a pin output to logic state Low.

This function should be used only for software driven pins. It does not have any effect on peripheral driven pins.

Parameters
basePointer to the pin's port register base address
pinNumPosition of the pin bit-field within the port register
Function Usage
/* Clear P0.3 (out value = Low) */
Cy_GPIO_Clr(P0_0_PORT, P0_0_NUM);

◆ Cy_GPIO_Inv()

__STATIC_INLINE void Cy_GPIO_Inv ( GPIO_PRT_Type base,
uint32_t  pinNum 
)

Set a pin output logic state to the inverse of the current output logic state.

This function should be used only for software driven pins. It does not have any effect on peripheral driven pins.

Parameters
basePointer to the pin's port register base address
pinNumPosition of the pin bit-field within the port register
Function Usage
/* Invert P0.3 (out value = ~(out value)) */
Cy_GPIO_Inv(P0_0_PORT, P0_0_NUM);

◆ Cy_GPIO_SetDrivemode()

__STATIC_INLINE void Cy_GPIO_SetDrivemode ( GPIO_PRT_Type base,
uint32_t  pinNum,
uint32_t  value 
)

Configures the pin output buffer drive mode and input buffer enable.

The output buffer drive mode and input buffer enable are combined into a single parameter. The drive mode controls the behavior of the pin in general. Enabling the input buffer allows the digital pin state to be read but also contributes to extra current consumption.

Parameters
basePointer to the pin's port register base address
pinNumPosition of the pin bit-field within the port register
valuePin drive mode. Options are detailed in Pin drive mode macros
Note
This function modifies a port register in a read-modify-write operation. It is not thread safe as the resource is shared among multiple pins on a port.
Function Usage
/* Scenario: Enter deep-sleep with reduced leakage current on P0.3 */
/* Get the drive mode of P0.3 */
if(CY_GPIO_DM_STRONG== Cy_GPIO_GetDrivemode(P0_0_PORT, P0_0_NUM))
{
/* Change the drive mode of P0.3 to analog (hi-z, input buffer off) */
Cy_GPIO_SetDrivemode(P0_0_PORT, P0_0_NUM, CY_GPIO_DM_ANALOG);
}

◆ Cy_GPIO_GetDrivemode()

__STATIC_INLINE uint32_t Cy_GPIO_GetDrivemode ( const GPIO_PRT_Type base,
uint32_t  pinNum 
)

Returns the pin output buffer drive mode and input buffer enable state.

Parameters
basePointer to the pin's port register base address
pinNumPosition of the pin bit-field within the port register
Returns
Pin drive mode. Options are detailed in Pin drive mode macros
Function Usage
/* Scenario: Enter deep-sleep with reduced leakage current on P0.3 */
/* Get the drive mode of P0.3 */
if(CY_GPIO_DM_STRONG== Cy_GPIO_GetDrivemode(P0_0_PORT, P0_0_NUM))
{
/* Change the drive mode of P0.3 to analog (hi-z, input buffer off) */
Cy_GPIO_SetDrivemode(P0_0_PORT, P0_0_NUM, CY_GPIO_DM_ANALOG);
}

◆ Cy_GPIO_SetVtrip()

__STATIC_INLINE void Cy_GPIO_SetVtrip ( GPIO_PRT_Type base,
uint32_t  value 
)

Configures the GPIO port input buffer voltage Threshold mode.

Parameters
basePointer to the pin's port register base address
valuePin voltage threshold mode. Options are detailed in Voltage trip mode macros
Note
This function modifies a port register in a read-modify-write operation. It is not thread safe as the resource is shared among multiple pins on a port.
Function Usage
/* Scenario: Connect the pin to a TTL hardware */
/* Get the vtrip value of P0.3 */
{
/* Change the vtrip of P0.3 to LVTTL */
}

◆ Cy_GPIO_GetVtrip()

__STATIC_INLINE uint32_t Cy_GPIO_GetVtrip ( const GPIO_PRT_Type base)

Returns the port input buffer voltage Threshold mode.

Parameters
basePointer to the pin's port register base address
Returns
Pin voltage threshold mode. Options are detailed in Voltage trip mode macros
Function Usage
/* Scenario: Connect the pin to a TTL hardware */
/* Get the vtrip value of P0.3 */
{
/* Change the vtrip of P0.3 to LVTTL */
}

◆ Cy_GPIO_SetSlewRate()

__STATIC_INLINE void Cy_GPIO_SetSlewRate ( GPIO_PRT_Type base,
uint32_t  value 
)

Configures the port output buffer slew rate.

Affects all the pins on the port.

Note
This function has no effect on GPIO ports where slew rate configuration is not available. For detail, refer to the device datasheet.
Parameters
baseThe pointer to the port's register base address
valuePort slew rate. Options are detailed in Slew Rate Mode macros
Note
This function modifies a port register in the read-modify-write operation. It is not thread-safe.
Function Usage
/* Scenario: Connect a pin to I2C (slow slew rate is preferred for low EMI) */
/* Get the slew rate value of P0.3 */
{
/* Change the slew rate of Port 0, which includes P0.3, to Slow */
}

◆ Cy_GPIO_GetSlewRate()

__STATIC_INLINE uint32_t Cy_GPIO_GetSlewRate ( const GPIO_PRT_Type base)

Returns the port output buffer slew rate.

Parameters
baseThe pointer to the port's register base address
Returns
The port slew rate. The options are detailed in the Slew Rate Mode macros
Function Usage
/* Scenario: Connect a pin to I2C (slow slew rate is preferred for low EMI) */
/* Get the slew rate value of P0.3 */
{
/* Change the slew rate of Port 0, which includes P0.3, to Slow */
}

◆ Cy_GPIO_MscControlEnable()

__STATIC_INLINE void Cy_GPIO_MscControlEnable ( const GPIO_PRT_Type base,
uint32_t  pinNum 
)

Enables control of the IO port analog signaling by the MSCV3LP IP block.

Parameters
basePointer to the pin's port register base address
pinNumPosition of the pin bit-field within the port register

◆ Cy_GPIO_MscControlDisable()

__STATIC_INLINE void Cy_GPIO_MscControlDisable ( const GPIO_PRT_Type base,
uint32_t  pinNum 
)

Disables control of the IO port analog signaling by the MSCV3LP IP block.

Parameters
basePointer to the pin's port register base address
pinNumPosition of the pin bit-field within the port register

◆ Cy_GPIO_MscControlIsEnabled()

__STATIC_INLINE bool Cy_GPIO_MscControlIsEnabled ( const GPIO_PRT_Type base,
uint32_t  pinNum 
)

Returns the enable status of by the MSCV3LP IP block control for that particular pin.

Parameters
basePointer to the pin's port register base address
pinNumPosition of the pin bit-field within the port register
Returns
Status of MSCV3LP IP block control over specified pin