DCHAN Enumerated Types

Enumerations
enum	cy_en_dsadc_dchan_decimator_sinc_mode_t {   CY_DSADC_DCHAN_DECIMATOR_SINC_MODE_SINC3 = 0U,   CY_DSADC_DCHAN_DECIMATOR_SINC_MODE_SINC4 = 1U }
	Decimator sinc filter modes. More...
enum	cy_en_dsadc_dchan_negative_pin_t {   CY_DSADC_DCHAN_NEGATIVE_PIN_VSSA = 0x00U,   CY_DSADC_DCHAN_NEGATIVE_PIN_VREFL = 0x09U,   CY_DSADC_DCHAN_NEGATIVE_PIN_SRSS_VSS = 0x0AU,   CY_DSADC_DCHAN_NEGATIVE_PIN_VDIV_RET = 0x0BU,   CY_DSADC_DCHAN_NEGATIVE_PIN_VTS_RET = 0x0CU,   CY_DSADC_DCHAN_NEGATIVE_PIN_VINT_RET = 0x0DU,   CY_DSADC_DCHAN_NEGATIVE_PIN_GPIO0 = 0x0EU,   CY_DSADC_DCHAN_NEGATIVE_PIN_GPIO2 = 0x0FU,   CY_DSADC_DCHAN_NEGATIVE_PIN_RSL_0 = 0x10U,   CY_DSADC_DCHAN_NEGATIVE_PIN_RSL_1 = 0x18U,   CY_DSADC_DCHAN_NEGATIVE_PIN_AMUXA = 0x1AU,   CY_DSADC_DCHAN_NEGATIVE_PIN_AMUXB = 0x1BU }
	Negative input pin selection for ADC. More...
enum	cy_en_dsadc_dchan_positive_pin_t {   CY_DSADC_DCHAN_POSITIVE_PIN_HVDIV0 = 0x0U,   CY_DSADC_DCHAN_POSITIVE_PIN_HVDIV1 = 0x04U,   CY_DSADC_DCHAN_POSITIVE_PIN_VTS = 0x08U,   CY_DSADC_DCHAN_POSITIVE_PIN_VINT = 0x0CU,   CY_DSADC_DCHAN_POSITIVE_PIN_VSSA = 0x10U,   CY_DSADC_DCHAN_POSITIVE_PIN_VSSD = 0x11U,   CY_DSADC_DCHAN_POSITIVE_PIN_VSSL = 0x12U,   CY_DSADC_DCHAN_POSITIVE_PIN_VREFL = 0x13U,   CY_DSADC_DCHAN_POSITIVE_PIN_VTS_RET_K = 0x15U,   CY_DSADC_DCHAN_POSITIVE_PIN_VINT_RET = 0x16U,   CY_DSADC_DCHAN_POSITIVE_PIN_VSUB = 0x17U,   CY_DSADC_DCHAN_POSITIVE_PIN_VCCD_DIV_2 = 0x18U,   CY_DSADC_DCHAN_POSITIVE_PIN_VCCHIB_DIV_2 = 0x19U,   CY_DSADC_DCHAN_POSITIVE_PIN_VDDA_DIV_4 = 0x1AU,   CY_DSADC_DCHAN_POSITIVE_PIN_VDDD_DIV_4 = 0x1BU,   CY_DSADC_DCHAN_POSITIVE_PIN_VREFH_1P2_HPBGR = 0x1CU,   CY_DSADC_DCHAN_POSITIVE_PIN_VREFH_0P8_HPBGR = 0x1DU,   CY_DSADC_DCHAN_POSITIVE_PIN_VREFH_0P7_HPBGR = 0x1EU,   CY_DSADC_DCHAN_POSITIVE_PIN_VREFH_1P2_SRSS = 0x1FU,   CY_DSADC_DCHAN_POSITIVE_PIN_GPIO0 = 0x20U,   CY_DSADC_DCHAN_POSITIVE_PIN_GPIO1 = 0x24U,   CY_DSADC_DCHAN_POSITIVE_PIN_GPIO2 = 0x28U,   CY_DSADC_DCHAN_POSITIVE_PIN_GPIO3 = 0x2CU,   CY_DSADC_DCHAN_POSITIVE_PIN_GPIO4 = 0x30U,   CY_DSADC_DCHAN_POSITIVE_PIN_GPIO5 = 0x34U,   CY_DSADC_DCHAN_POSITIVE_PIN_GPIO6 = 0x38U,   CY_DSADC_DCHAN_POSITIVE_PIN_GPIO7 = 0x3CU,   CY_DSADC_DCHAN_POSITIVE_PIN_RSH_0 = 0x40U,   CY_DSADC_DCHAN_POSITIVE_PIN_RSH_1 = 0x60U,   CY_DSADC_DCHAN_POSITIVE_PIN_AMUXA = 0x7AU,   CY_DSADC_DCHAN_POSITIVE_PIN_AMUXB = 0x7BU }
	Select the positive input pin for the DCHAN while the DCHAN is being scanned. More...
enum	cy_en_dsadc_dchan_post_processing_range_conditional_t {   CY_DSADC_DCHAN_RANGE_CONDITIONAL_LESS_THAN = 0U,   CY_DSADC_DCHAN_RANGE_CONDITIONAL_BETWEEN = 1U,   CY_DSADC_DCHAN_RANGE_CONDITIONAL_GREATER_THAN = 2U,   CY_DSADC_DCHAN_RANGE_CONDITIONAL_OUTSIDE = 3U }
	Select the condition in which the Range Condition interrupt is triggered. More...
enum	cy_en_dsadc_dchan_post_processing_range_mode_t {   CY_DSADC_DCHAN_RANGE_MODE_DISABLE = 0U,   CY_DSADC_DCHAN_RANGE_MODE_SIMPLE = 1U,   CY_DSADC_DCHAN_RANGE_MODE_EVENT_COUNT = 2U }
	Enable / Configure the Range Detection Mode. More...
enum	cy_en_dsadc_dchan_priority_t {   CY_DSADC_DCHAN_PRIORITY_PRIMARY = 0U,   CY_DSADC_DCHAN_PRIORITY_SECONDARY = 1U }
	Priority settings for the digital channel. More...
enum	cy_en_dsadc_dchan_reference_pullup_t {   CY_DSADC_DCHAN_REFERENCE_PULLUP_RSH1 = 0U,   CY_DSADC_DCHAN_REFERENCE_PULLUP_RSH0 = 1U,   CY_DSADC_DCHAN_REFERENCE_PULLUP_RSL1 = 2U,   CY_DSADC_DCHAN_REFERENCE_PULLUP_RSL0 = 3U }
	Configure the RS open detection pull-up selection. More...
enum	cy_en_dsadc_dchan_reference_vrefh_t {   CY_DSADC_DCHAN_REFERENCE_VREFH_DIRECT = 0U,   CY_DSADC_DCHAN_REFERENCE_VREFH_BUFFERED = 1U,   CY_DSADC_DCHAN_REFERENCE_VREFH_SRSS = 2U,   CY_DSADC_DCHAN_REFERENCE_VREFH_VTS_REF = 3U,   CY_DSADC_DCHAN_REFERENCE_VREFH_VDDA_DIV_4 = 4U,   CY_DSADC_DCHAN_REFERENCE_VREFH_VDDA_DIV_3 = 5U }
	Configure the VREF High selection. More...
enum	cy_en_dsadc_dchan_reference_vrefl_t {   CY_DSADC_DCHAN_REFERENCE_VREFL_VREFL = 0U,   CY_DSADC_DCHAN_REFERENCE_VREFL_VSSA_SRSS = 1U,   CY_DSADC_DCHAN_REFERENCE_VREFL_VSSA_KELVIN = 2U,   CY_DSADC_DCHAN_REFERENCE_VREFL_VTS_RET = 3U }
	Configure the VREF Low selection. More...
enum	cy_en_dsadc_dchan_sample_mode_t {   CY_DSADC_DCHAN_SAMPLE_MODE_SINGLE_SHOT = 0U,   CY_DSADC_DCHAN_SAMPLE_MODE_CONTINUOUS = 1U }
	Sample mode for the digital channel. More...
enum	cy_en_dsadc_dchan_achan_select_t {   CY_DSADC_DCHAN_SELECT_ACHAN0 = 0U,   CY_DSADC_DCHAN_SELECT_ACHAN1 = 1U }
	Select the Analog Channel to use from the Digital Channel Configuration. More...
enum	cy_en_dsadc_averaging_samples_t {   CY_DSADC_AVERAGING_SAMPLES_NONE = 0U,   CY_DSADC_AVERAGING_SAMPLES_2 = 1U,   CY_DSADC_AVERAGING_SAMPLES_4 = 2U }
	Set the number of samples to average or accumulated in DCHAN post processing. More...
enum	cy_en_dsadc_agc_fast_decimator_scaler_t {   CY_DSADC_AGC_FAST_DECIMATOR_SCALER_1 = 0U,   CY_DSADC_AGC_FAST_DECIMATOR_SCALER_2 = 1U,   CY_DSADC_AGC_FAST_DECIMATOR_SCALER_4 = 2U,   CY_DSADC_AGC_FAST_DECIMATOR_SCALER_8 = 3U }
	Configure fast decimator scaler. More...
enum	cy_en_dsadc_agc_threshold_filter_mode_t {   CY_DSADC_AGC_THRESHOLD_FILTER_MODE_COUNTER = 0U,   CY_DSADC_AGC_THRESHOLD_FILTER_MODE_INTEGRATOR = 1U }
	Configure threshold filter mode. More...
enum	cy_en_dsadc_averaging_mode_t {   CY_DSADC_AVERAGING_MODE_AVERAGE = 0U,   CY_DSADC_AVERAGING_MODE_ACCUMULATE = 1U }
	Configure the averaging mode. More...
enum	cy_en_dsadc_aaf_mode_t {   CY_DSADC_AAF_BYPASS = 0U,   CY_DSADC_AAF_ENABLE = 1U,   CY_DSADC_AAF_SHORT_ON_SELECT = 2U }
	Selection describes how the Anti-Aliasing Filter will be used by the channel. More...

Detailed Description

Enumeration Type Documentation

cy_en_dsadc_dchan_decimator_sinc_mode_t

enum cy_en_dsadc_dchan_decimator_sinc_mode_t

Decimator sinc filter modes.

Enumerator
CY_DSADC_DCHAN_DECIMATOR_SINC_MODE_SINC3	Set the Decimator sinc filter to 'Sinc3'.
CY_DSADC_DCHAN_DECIMATOR_SINC_MODE_SINC4	Set the Decimator sinc filter to 'Sinc4'.

cy_en_dsadc_dchan_negative_pin_t

enum cy_en_dsadc_dchan_negative_pin_t

Negative input pin selection for ADC.

Enumerator
CY_DSADC_DCHAN_NEGATIVE_PIN_VSSA	VSSA.
CY_DSADC_DCHAN_NEGATIVE_PIN_VREFL	Voltage Reference Low Connection.
CY_DSADC_DCHAN_NEGATIVE_PIN_SRSS_VSS	VDIV_RET.
CY_DSADC_DCHAN_NEGATIVE_PIN_VDIV_RET	SRSS Ground (VSS)
CY_DSADC_DCHAN_NEGATIVE_PIN_VTS_RET	External Temperature Sensor Return.
CY_DSADC_DCHAN_NEGATIVE_PIN_VINT_RET	Internal Temperature Sensor Return.
CY_DSADC_DCHAN_NEGATIVE_PIN_GPIO0	GPIO 0 (P0_0)
CY_DSADC_DCHAN_NEGATIVE_PIN_GPIO2	GPIO 2 (P0_2)
CY_DSADC_DCHAN_NEGATIVE_PIN_RSL_0	Low Side of Shunt Resistor Zero.
CY_DSADC_DCHAN_NEGATIVE_PIN_RSL_1	Low Side of Shunt Resistor One.
CY_DSADC_DCHAN_NEGATIVE_PIN_AMUXA	AMUXA Bus.
CY_DSADC_DCHAN_NEGATIVE_PIN_AMUXB	AMUXB Bus.

cy_en_dsadc_dchan_positive_pin_t

enum cy_en_dsadc_dchan_positive_pin_t

Select the positive input pin for the DCHAN while the DCHAN is being scanned.

Enumerator
CY_DSADC_DCHAN_POSITIVE_PIN_HVDIV0	Set the positive input pin to the output of high voltage divider 0 (HVDIV0 or VSENSE).
CY_DSADC_DCHAN_POSITIVE_PIN_HVDIV1	Set the positive input pin to the output of high voltage divider 1 (HVDIV1 or VDIAG).
CY_DSADC_DCHAN_POSITIVE_PIN_VTS	Set the positive input pin to the external temperature sensor pin. (P1_1)
CY_DSADC_DCHAN_POSITIVE_PIN_VINT	Internal Temperature Sensor Input.
CY_DSADC_DCHAN_POSITIVE_PIN_VSSA	Ground Connection Analog (VSSA)
CY_DSADC_DCHAN_POSITIVE_PIN_VSSD	Ground Connection Digital (VSSD)
CY_DSADC_DCHAN_POSITIVE_PIN_VSSL	High Voltage Subsystem ground connection.
CY_DSADC_DCHAN_POSITIVE_PIN_VREFL	Voltage Reference Low connection.
CY_DSADC_DCHAN_POSITIVE_PIN_VTS_RET_K	External Temperature Sensor Return Kelvin, equivalent to VTS_RET.
CY_DSADC_DCHAN_POSITIVE_PIN_VINT_RET	Internal Temperature Sensor Return.
CY_DSADC_DCHAN_POSITIVE_PIN_VSUB	VSUB.
CY_DSADC_DCHAN_POSITIVE_PIN_VCCD_DIV_2	VCCD / 2.
CY_DSADC_DCHAN_POSITIVE_PIN_VCCHIB_DIV_2	High Voltage Input Bus VCCD / 2.
CY_DSADC_DCHAN_POSITIVE_PIN_VDDA_DIV_4	VDDA / 4.
CY_DSADC_DCHAN_POSITIVE_PIN_VDDD_DIV_4	VDDD / 4.
CY_DSADC_DCHAN_POSITIVE_PIN_VREFH_1P2_HPBGR	1.2 V HPBGR Voltage Reference High connection
CY_DSADC_DCHAN_POSITIVE_PIN_VREFH_0P8_HPBGR	0.8 V HPBGR Voltage Reference High connection
CY_DSADC_DCHAN_POSITIVE_PIN_VREFH_0P7_HPBGR	0.7 V HPBGR Voltage Reference High connection
CY_DSADC_DCHAN_POSITIVE_PIN_VREFH_1P2_SRSS	1.2 V SRSS Voltage Reference High connection
CY_DSADC_DCHAN_POSITIVE_PIN_GPIO0	GPIO 0 Connection (P0_0)
CY_DSADC_DCHAN_POSITIVE_PIN_GPIO1	GPIO 1 Connection (P0_1)
CY_DSADC_DCHAN_POSITIVE_PIN_GPIO2	GPIO 2 Connection (P0_2)
CY_DSADC_DCHAN_POSITIVE_PIN_GPIO3	GPIO 3 Connection (P0_3)
CY_DSADC_DCHAN_POSITIVE_PIN_GPIO4	GPIO 4 Connection (P0_4)
CY_DSADC_DCHAN_POSITIVE_PIN_GPIO5	GPIO 5 Connection (P0_5)
CY_DSADC_DCHAN_POSITIVE_PIN_GPIO6	GPIO 6 Connection (P0_6)
CY_DSADC_DCHAN_POSITIVE_PIN_GPIO7	GPIO 7 Connection (P0_7)
CY_DSADC_DCHAN_POSITIVE_PIN_RSH_0	Shunt Resistor Zero High Side.
CY_DSADC_DCHAN_POSITIVE_PIN_RSH_1	Shunt Resistor One High Side.
CY_DSADC_DCHAN_POSITIVE_PIN_AMUXA	Analog Mux Bus A.
CY_DSADC_DCHAN_POSITIVE_PIN_AMUXB	Analog Mux Bus B.

cy_en_dsadc_dchan_post_processing_range_conditional_t

enum cy_en_dsadc_dchan_post_processing_range_conditional_t

Select the condition in which the Range Condition interrupt is triggered.

Enumerator
CY_DSADC_DCHAN_RANGE_CONDITIONAL_LESS_THAN	Triggered when the result is less than the Lower Range Threshold (result < LOWER_RANGE)
CY_DSADC_DCHAN_RANGE_CONDITIONAL_BETWEEN	Triggered when the result is between the lower and upper range thresholds (LOWER_RANGE <= result < UPPER_RANGE)
CY_DSADC_DCHAN_RANGE_CONDITIONAL_GREATER_THAN	Triggered when the result is greater than the upper threshold (UPPER_RANGE <= result)
CY_DSADC_DCHAN_RANGE_CONDITIONAL_OUTSIDE	Triggered when the result is lower than the Lower Range Threshold or greater than the upper range threshold (LOWER_RANGE > result || UPPER_RANGE <= result)

cy_en_dsadc_dchan_post_processing_range_mode_t

enum cy_en_dsadc_dchan_post_processing_range_mode_t

Enable / Configure the Range Detection Mode.

Enumerator
CY_DSADC_DCHAN_RANGE_MODE_DISABLE	Disable range detection.
CY_DSADC_DCHAN_RANGE_MODE_SIMPLE	Enable range detection.
CY_DSADC_DCHAN_RANGE_MODE_EVENT_COUNT	Enable range detection with event filtering counter.

cy_en_dsadc_dchan_priority_t

enum cy_en_dsadc_dchan_priority_t

Priority settings for the digital channel.

Enumerator
CY_DSADC_DCHAN_PRIORITY_PRIMARY	Primary priority. Does not respond to secondary triggers.
CY_DSADC_DCHAN_PRIORITY_SECONDARY	Secondary priority. When a secondary trigger is received, queue this channel to be used in a conversion after the next primary conversion finishes.

cy_en_dsadc_dchan_reference_pullup_t

enum cy_en_dsadc_dchan_reference_pullup_t

Configure the RS open detection pull-up selection.

Enumerator
CY_DSADC_DCHAN_REFERENCE_PULLUP_RSH1	Connect RSH[1] to the 4k pull-up to VDDA.
CY_DSADC_DCHAN_REFERENCE_PULLUP_RSH0	Connect RSH[0] to the 4k pull-up to VDDA.
CY_DSADC_DCHAN_REFERENCE_PULLUP_RSL1	Connect RSL[1] to the 4k pull-up to VDDA.
CY_DSADC_DCHAN_REFERENCE_PULLUP_RSL0	Connect RSL[0] to the 4k pull-up to VDDA.

cy_en_dsadc_dchan_reference_vrefh_t

enum cy_en_dsadc_dchan_reference_vrefh_t

Configure the VREF High selection.

Enumerator
CY_DSADC_DCHAN_REFERENCE_VREFH_DIRECT	High-Precision BandGap Reference (HPBGR)
CY_DSADC_DCHAN_REFERENCE_VREFH_BUFFERED	High-Precision BandGap Reference (HPBGR) buffered.
CY_DSADC_DCHAN_REFERENCE_VREFH_SRSS	SRSS.
CY_DSADC_DCHAN_REFERENCE_VREFH_VTS_REF	Temperature Sensor common connection.
CY_DSADC_DCHAN_REFERENCE_VREFH_VDDA_DIV_4	VDDA / 4.
CY_DSADC_DCHAN_REFERENCE_VREFH_VDDA_DIV_3	VDDA / 3.

cy_en_dsadc_dchan_reference_vrefl_t

enum cy_en_dsadc_dchan_reference_vrefl_t

Configure the VREF Low selection.

Enumerator
CY_DSADC_DCHAN_REFERENCE_VREFL_VREFL	VREFL input from pad, treated as a ground.
CY_DSADC_DCHAN_REFERENCE_VREFL_VSSA_SRSS	The VSSA Connection from the SRSS.
CY_DSADC_DCHAN_REFERENCE_VREFL_VSSA_KELVIN	The VSSA Connection from the Temperature.
CY_DSADC_DCHAN_REFERENCE_VREFL_VTS_RET	Temperature Sensor return connection.

cy_en_dsadc_dchan_sample_mode_t

enum cy_en_dsadc_dchan_sample_mode_t

Sample mode for the digital channel.

Enumerator
CY_DSADC_DCHAN_SAMPLE_MODE_SINGLE_SHOT	The channel will do a single conversion after it receives a trigger.
CY_DSADC_DCHAN_SAMPLE_MODE_CONTINUOUS	The channel will do back-to-back conversions after it is triggered once.

cy_en_dsadc_dchan_achan_select_t

enum cy_en_dsadc_dchan_achan_select_t

Select the Analog Channel to use from the Digital Channel Configuration.

Enumerator
CY_DSADC_DCHAN_SELECT_ACHAN0	Select Analog Channel 0.
CY_DSADC_DCHAN_SELECT_ACHAN1	Select Analog Channel 1.

cy_en_dsadc_averaging_samples_t

enum cy_en_dsadc_averaging_samples_t

Set the number of samples to average or accumulated in DCHAN post processing.

Enumerator
CY_DSADC_AVERAGING_SAMPLES_NONE	Disable Averaging / Accumulating.
CY_DSADC_AVERAGING_SAMPLES_2	Average or Accumulate 2 samples.
CY_DSADC_AVERAGING_SAMPLES_4	Average or Accumulate 4 samples.

cy_en_dsadc_agc_fast_decimator_scaler_t

enum cy_en_dsadc_agc_fast_decimator_scaler_t

Configure fast decimator scaler.

Enumerator
CY_DSADC_AGC_FAST_DECIMATOR_SCALER_1	FAST_DEC_RESULT is same as result (FAST_DEC_RESULT = RESULT).
CY_DSADC_AGC_FAST_DECIMATOR_SCALER_2	FAST_DEC_RESULT is 2 times of result (FAST_DEC_RESULT = RESULT << 1).
CY_DSADC_AGC_FAST_DECIMATOR_SCALER_4	FAST_DEC_RESULT is 4 times of result (FAST_DEC_RESULT = RESULT << 2)
CY_DSADC_AGC_FAST_DECIMATOR_SCALER_8	FAST_DEC_RESULT is 8 times of result (FAST_DEC_RESULT = RESULT << 3)

cy_en_dsadc_agc_threshold_filter_mode_t

enum cy_en_dsadc_agc_threshold_filter_mode_t

Configure threshold filter mode.

Enumerator
CY_DSADC_AGC_THRESHOLD_FILTER_MODE_COUNTER	Set counter mode.
CY_DSADC_AGC_THRESHOLD_FILTER_MODE_INTEGRATOR	Set integrator mode.

cy_en_dsadc_averaging_mode_t

enum cy_en_dsadc_averaging_mode_t

Configure the averaging mode.

Enumerator
CY_DSADC_AVERAGING_MODE_AVERAGE	Average the set number of samples in the result register.
CY_DSADC_AVERAGING_MODE_ACCUMULATE	Accumulate the number of samples in the result register.

cy_en_dsadc_aaf_mode_t

enum cy_en_dsadc_aaf_mode_t

Selection describes how the Anti-Aliasing Filter will be used by the channel.

Enumerator
CY_DSADC_AAF_BYPASS	Anti-Aliasing Filter will be bypassed.
CY_DSADC_AAF_ENABLE	Anti-Aliasing Filter will be used continually.
CY_DSADC_AAF_SHORT_ON_SELECT	Anti-Aliasing Filter will be pre-charged during channel select delay and used normally afterward.