Interrupt Cause Masks

Macros
#define	CY_DSADC_MMIO_INTR_CAUSE_DCH0   (PACSS_MMIO_INTR_CAUSE_DCH0_INT_Msk)
	Interrupt MMIO cause masks. More...
#define	CY_DSADC_MMIO_INTR_CAUSE_DCH1   (PACSS_MMIO_INTR_CAUSE_DCH1_INT_Msk)
	Interrupt cause is DCHAN 1 Interrupt Pending.
#define	CY_DSADC_MMIO_INTR_CAUSE_DCH2   (PACSS_MMIO_INTR_CAUSE_DCH2_INT_Msk)
	Interrupt cause is DCHAN 2 Interrupt Pending.
#define	CY_DSADC_MMIO_INTR_CAUSE_DCH3   (PACSS_MMIO_INTR_CAUSE_DCH3_INT_Msk)
	Interrupt cause is DCHAN 3 Interrupt Pending.
#define	CY_DSADC_MMIO_INTR_CAUSE_PACSS   (PACSS_MMIO_INTR_CAUSE_PACSS_INT_Msk)
	Interrupt cause is System (PACSS_MMIO) Interrupt Pending.
#define	CY_DSADC_INTR_CAUSE_MASK
	Combined interrupt cause mask. More...

Detailed Description

Macro Definition Documentation

CY_DSADC_MMIO_INTR_CAUSE_DCH0

#define CY_DSADC_MMIO_INTR_CAUSE_DCH0   (PACSS_MMIO_INTR_CAUSE_DCH0_INT_Msk)

Interrupt MMIO cause masks.

Interrupt cause is DCHAN 0 Interrupt Pending

CY_DSADC_INTR_CAUSE_MASK

#define CY_DSADC_INTR_CAUSE_MASK

Value:

(CY_DSADC_MMIO_INTR_CAUSE_DCH0 | \
                                             CY_DSADC_MMIO_INTR_CAUSE_DCH1 | \
                                             CY_DSADC_MMIO_INTR_CAUSE_DCH2 | \
                                             CY_DSADC_MMIO_INTR_CAUSE_DCH3 | \
                                             CY_DSADC_MMIO_INTR_CAUSE_PACSS)

Combined interrupt cause mask.