Macros | |
#define | CY_DMAC_INTR_CHAN_0 (0x1UL) |
Channel 0 interrupt mask. | |
#define | CY_DMAC_INTR_CHAN_1 (0x2UL) |
Channel 1 interrupt mask. | |
#define | CY_DMAC_INTR_CHAN_2 (0x4UL) |
Channel 2 interrupt mask. | |
#define | CY_DMAC_INTR_CHAN_3 (0x8UL) |
Channel 3 interrupt mask. | |
#define | CY_DMAC_INTR_CHAN_4 (0x10UL) |
Channel 4 interrupt mask. | |
#define | CY_DMAC_INTR_CHAN_5 (0x20UL) |
Channel 5 interrupt mask. | |
#define | CY_DMAC_INTR_CHAN_6 (0x40UL) |
Channel 6 interrupt mask. | |
#define | CY_DMAC_INTR_CHAN_7 (0x80UL) |
Channel 7 interrupt mask. | |
#define | CY_DMAC_INTR_CHAN_8 (0x100UL) |
Channel 8 interrupt mask. | |
#define | CY_DMAC_INTR_CHAN_9 (0x200UL) |
Channel 9 interrupt mask. | |
#define | CY_DMAC_INTR_CHAN_10 (0x400UL) |
Channel 10 interrupt mask. | |
#define | CY_DMAC_INTR_CHAN_11 (0x800UL) |
Channel 11 interrupt mask. | |
#define | CY_DMAC_INTR_CHAN_12 (0x1000UL) |
Channel 12 interrupt mask. | |
#define | CY_DMAC_INTR_CHAN_13 (0x2000UL) |
Channel 13 interrupt mask. | |
#define | CY_DMAC_INTR_CHAN_14 (0x4000UL) |
Channel 14 interrupt mask. | |
#define | CY_DMAC_INTR_CHAN_15 (0x8000UL) |
Channel 15 interrupt mask. | |