SAR Sequencer Controlled Switch Macros

Macros
#define	CY_CTB_SW_HW_CTRL_D51   (CTBM_CTB_SW_HW_CTRL_P2_HW_CTRL_Msk)
	Masks for CTB switches that can be controlled by the hardware These masks are used in Cy_CTB_EnableSarSeqCtrl and Cy_CTB_DisableSarSeqCtrl. More...
#define	CY_CTB_SW_HW_CTRL_D52_D62   (CTBM_CTB_SW_HW_CTRL_P3_HW_CTRL_Msk)
	Enable hardware control of the D52 and D62 switches.
#define	CY_CTB_SW_HW_CTRL_D51_D52_D62   (CTBM_CTB_SW_HW_CTRL_P2_HW_CTRL_Msk | CTBM_CTB_SW_HW_CTRL_P3_HW_CTRL_Msk)
	Enable hardware control of all three switches.

Detailed Description

Macro Definition Documentation

CY_CTB_SW_HW_CTRL_D51

#define CY_CTB_SW_HW_CTRL_D51   (CTBM_CTB_SW_HW_CTRL_P2_HW_CTRL_Msk)

Masks for CTB switches that can be controlled by the hardware These masks are used in Cy_CTB_EnableSarSeqCtrl and Cy_CTB_DisableSarSeqCtrl.

The SAR ADC subsystem supports analog routes through three CTB switches on SARBUS0 and SARBUS1. This control allows for pins on the CTB dedicated port to route to the SAR ADC input channels:

• D51: Connects the inverting terminal of OA0 to SARBUS0
• D52: Connects the inverting terminal of OA1 to SARBUS0
• D62: Connects the inverting terminal of OA1 to SARBUS1Enable hardware control of the D51 switch