MTB CAT1 Peripheral driver library
cy_stc_smif_config_t Struct Reference

Description

The SMIF configuration structure.

Data Fields

uint32_t mode
 Specifies the mode of operation cy_en_smif_mode_t. More...
 
uint32_t deselectDelay
 Specifies the minimum duration of SPI de-selection between SPI transfers: More...
 
uint32_t rxClockSel
 Specifies the clock source for the receiver clock cy_en_smif_clk_select_t. More...
 
uint32_t blockEvent
 Specifies what happens when there is a Read from an empty RX FIFO or a Write to a full TX FIFO. More...
 
cy_en_smif_delay_tap_t delayTapEnable
 Delay tap can be enabled or disabled cy_en_smif_delay_tap_t. More...
 
cy_en_smif_delay_line_t delayLineSelect
 set line selection which is input. More...
 

Field Documentation

◆ mode

uint32_t cy_stc_smif_config_t::mode

Specifies the mode of operation cy_en_smif_mode_t.

◆ deselectDelay

uint32_t cy_stc_smif_config_t::deselectDelay

Specifies the minimum duration of SPI de-selection between SPI transfers:

  • "0": 1 clock cycle.
  • "1": 2 clock cycles.
  • "2": 3 clock cycles.
  • "3": 4 clock cycles.
  • "4": 5 clock cycles.
  • "5": 6 clock cycles.
  • "6": 7 clock cycles.
  • "7": 8 clock cycles.

◆ rxClockSel

uint32_t cy_stc_smif_config_t::rxClockSel

Specifies the clock source for the receiver clock cy_en_smif_clk_select_t.

Used for CAT1A, CAT1B and CAT1C devices.

◆ blockEvent

uint32_t cy_stc_smif_config_t::blockEvent

Specifies what happens when there is a Read from an empty RX FIFO or a Write to a full TX FIFO.

cy_en_smif_error_event_t.

◆ delayTapEnable

cy_en_smif_delay_tap_t cy_stc_smif_config_t::delayTapEnable

Delay tap can be enabled or disabled cy_en_smif_delay_tap_t.

◆ delayLineSelect

cy_en_smif_delay_line_t cy_stc_smif_config_t::delayLineSelect

set line selection which is input.

cy_en_smif_delay_line_t