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MTB CAT1 Peripheral driver library
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MTB CAT1 Peripheral driver library
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PDM-PCM initialization configuration.
Data Fields | |
| uint8_t | clkDiv |
| PDM Clock Divider This configures a frequency of PDM CLK. More... | |
| cy_en_pdm_pcm_clock_sel_t | clksel |
| Interface clock clk_if selection. More... | |
| cy_en_pdm_pcm_halve_rate_sel_t | halverate |
| Halve rate sampling. More... | |
| uint8_t | route |
| Specifies what IOSS data input signal "pdm_data[]" is routed to a specific PDM receiver. More... | |
| uint8_t | fir0_coeff_user_value |
| FIR 0 filter coefficient enable. More... | |
| uint8_t | fir1_coeff_user_value |
| FIR 1 filter coefficient enable. More... | |
| cy_stc_pdm_pcm_fir_coeff_t | fir0_coeff [8] |
| The (symmetric) 30-taps finite impulse response (FIR) filter with 14-bit signed coefficients (in the range [-8192, 8191]) are specified by FIR0_COEFF0, ..., FIR0_COEFF7. More... | |
| cy_stc_pdm_pcm_fir_coeff_t | fir1_coeff [14] |
| The (symmetric) 55-taps finite impulse response (FIR) filter with 14-bit signed coefficients (in the range [-8192, 8191]) are specified by FIR1_COEFF0, ..., FIR1_COEFF13. More... | |
| uint8_t cy_stc_pdm_pcm_config_v2_t::clkDiv |
PDM Clock Divider This configures a frequency of PDM CLK.
The configured frequency is used to operate PDM core. The value that user assigns here will be incremented by 1 and assigned internally. For example, if the clkDiv value is 0, it is internally incremented by 1.
| cy_en_pdm_pcm_clock_sel_t cy_stc_pdm_pcm_config_v2_t::clksel |
Interface clock clk_if selection.
| cy_en_pdm_pcm_halve_rate_sel_t cy_stc_pdm_pcm_config_v2_t::halverate |
Halve rate sampling.
| uint8_t cy_stc_pdm_pcm_config_v2_t::route |
Specifies what IOSS data input signal "pdm_data[]" is routed to a specific PDM receiver.
Each PDM receiver j has a dedicated 1-bit control field: PDM receiver j uses DATA_SEL[j]. The 1-bit field DATA_SEL[j] specification is as follows: '0': PDM receiver j uses data input signal "pdm_data[j]". '1': PDM receiver j uses data input signal "pdm_data[j ^ 1]" (the lower bit of the index is inverted)
| uint8_t cy_stc_pdm_pcm_config_v2_t::fir0_coeff_user_value |
FIR 0 filter coefficient enable.
User has to configure the coeff values. 0: Disabled. 1: Enabled
| uint8_t cy_stc_pdm_pcm_config_v2_t::fir1_coeff_user_value |
FIR 1 filter coefficient enable.
User has to configure the coeff values. 0: Disabled. 1: Enabled
| cy_stc_pdm_pcm_fir_coeff_t cy_stc_pdm_pcm_config_v2_t::fir0_coeff[8] |
The (symmetric) 30-taps finite impulse response (FIR) filter with 14-bit signed coefficients (in the range [-8192, 8191]) are specified by FIR0_COEFF0, ..., FIR0_COEFF7.
The FIR filter coefficients have no default values: the coefficients MUST be programmed BEFORE the filter is enabled. By Default FIR0 is disabled and is only used for 8Khz and 16 Khz sample frequencies
| cy_stc_pdm_pcm_fir_coeff_t cy_stc_pdm_pcm_config_v2_t::fir1_coeff[14] |
The (symmetric) 55-taps finite impulse response (FIR) filter with 14-bit signed coefficients (in the range [-8192, 8191]) are specified by FIR1_COEFF0, ..., FIR1_COEFF13.
The (default) FIR filter has built in droop correction. The filter gain (sum of the coefficients) is 13921 and the default coefficients (as specified by FIR1_COEFFx.DATA0/1[13:0]) are: (-2, 21), (26, -17), (-41, 25), (68, -33), (-107, 41), (160, -48), (-230, 54), (325, -56), (-453, 51), (631, -31), (-894, -21), (1326, 172), (-2191, -770), (4859, 8191)