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MTB CAT1 Peripheral driver library
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MTB CAT1 Peripheral driver library
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Ethernet MAC detailed configurations.
Data Fields | |
| bool | bintrEnable |
| interrupts/events to enable on start | |
| cy_en_ethif_dma_data_buffer_len_t | dmaDataBurstLen |
| fixed burst length for DMA data transfers More... | |
| uint8_t | u8dmaCfgFlags |
| DMA config register bits 24, 25 & 26. More... | |
| cy_en_ethif_dma_mdc_clk_div_t | mdcPclkDiv |
| divisor to generate MDC from pclk More... | |
| uint8_t | u8rxLenErrDisc |
| enable discard of frames with length field error | |
| uint8_t | u8disCopyPause |
| disable copying Rx pause frames to memory | |
| uint8_t | u8chkSumOffEn |
| enable checksum offload operation | |
| uint8_t | u8rx1536ByteEn |
| enable Rx of frames up to 1536 bytes | |
| uint8_t | u8rxJumboFrEn |
| enable Rx of jumbo frames | |
| uint8_t | u8enRxBadPreamble |
| enable Rx frames with non-standard preamble | |
| uint8_t | u8ignoreIpgRxEr |
| ignore IPG rx_er (NetCfg b30) | |
| uint8_t | u8storeUdpTcpOffset |
| u8storeUdpTcpOffset | |
| uint8_t | u8aw2wMaxPipeline |
| Maximum number of outstanding AXI write requests, that can be issued by DMA via the AW channel. More... | |
| uint8_t | u8ar2rMaxPipeline |
| Maximum number of outstanding AXI read requests, that can be issued by DMA via the AR channel. More... | |
| uint8_t | u8pfcMultiQuantum |
| enable pfc multiple quantum (8 different priorities) | |
| cy_stc_ethif_wrapper_config_t * | pstcWrapperConfig |
| Configuration for Wrapper. | |
| cy_stc_ethif_tsu_config_t * | pstcTSUConfig |
| Configuration for TSU. | |
| bool | btxq0enable |
| Tx Q0 Enable. | |
| bool | btxq1enable |
| Tx Q1 Enable. | |
| bool | btxq2enable |
| Tx Q2 Enable. | |
| bool | brxq0enable |
| Rx Q0 Enable. | |
| bool | brxq1enable |
| Rx Q1 Enable. | |
| bool | brxq2enable |
| Rx Q2 Enable. | |
| cy_ethif_buffpool_t * | pRxQbuffPool [CY_ETH_DEFINE_NUM_RXQS] |
| Rx Queues buffer pool 32 bytes aligned. | |
| cy_en_ethif_dma_data_buffer_len_t cy_stc_ethif_mac_config_t::dmaDataBurstLen |
fixed burst length for DMA data transfers
bit4:0 amba_burst_length 1xxxx: attempt use burst up to 16 (CY_ETHIF_DMA_DBUR_LEN_16) 01xxx: attempt use burst up to 8 (CY_ETHIF_DMA_DBUR_LEN_8) 001xx: attempt use burst up to 4 (CY_ETHIF_DMA_DBUR_LEN_4) 0001x: always use single burst 00001: always use single burst (CY_ETHIF_AMBD_BURST_LEN_1) 00000: best AXI burst up to 256 beats
| uint8_t cy_stc_ethif_mac_config_t::u8dmaCfgFlags |
DMA config register bits 24, 25 & 26.
OR the following bit-flags to set corresponding bits - CY_ETHIF_CFG_DMA_DISC_RXP, CY_ETHIF_CFG_DMA_FRCE_RX_BRST, CY_ETHIF_CFG_DMA_FRCE_TX_BRST
| cy_en_ethif_dma_mdc_clk_div_t cy_stc_ethif_mac_config_t::mdcPclkDiv |
divisor to generate MDC from pclk
CY_ETHIF_MDC_DIV_BY_8 = 0 CY_ETHIF_MDC_DIV_BY_16 = 1 CY_ETHIF_MDC_DIV_BY_32 = 2 CY_ETHIF_MDC_DIV_BY_48 = 3 CY_ETHIF_MDC_DIV_BY_64 = 4 CY_ETHIF_MDC_DIV_BY_96 = 5 CY_ETHIF_MDC_DIV_BY_128 = 6 CY_ETHIF_MDC_DIV_BY_224 = 7
| uint8_t cy_stc_ethif_mac_config_t::u8aw2wMaxPipeline |
Maximum number of outstanding AXI write requests, that can be issued by DMA via the AW channel.
Must not be = 0 if using AXI as this would disable writes
| uint8_t cy_stc_ethif_mac_config_t::u8ar2rMaxPipeline |
Maximum number of outstanding AXI read requests, that can be issued by DMA via the AR channel.
Must not be = 0 if using AXI as this would disable reads