Description

Configuration structure to set up the entire CTDAC block to be used with Cy_CTDAC_Init.

Data Fields
cy_en_ctdac_ref_source_t	refSource
	Reference source: Vdda or externally through Opamp1 of CTB.

cy_en_ctdac_format_t	formatMode
	Format of DAC value: signed or unsigned.

cy_en_ctdac_update_t	updateMode
	Update mode: direct or buffered writes or hardware, edge or level.

cy_en_ctdac_deglitch_t	deglitchMode
	Deglitch mode: disabled, buffered, unbuffered, or both.

cy_en_ctdac_output_mode_t	outputMode
	Output mode: enabled (value or value + 1), high-z, Vssa, or Vdda.

cy_en_ctdac_output_buffer_t	outputBuffer
	Output path: Buffered through Opamp0 of CTB or connected directly to Pin 6.

cy_en_ctdac_deep_sleep_t	deepSleep
	Enable or disable the CTDAC during Deep Sleep.

uint32_t	deglitchCycles
	Number of deglitch cycles from 0 to 63.

int32_t	value
	Current DAC value.

int32_t	nextValue
	Next DAC value for double buffering.

bool	enableInterrupt
	If true, enable interrupt when next value register is transferred to value register.

bool	configClock
	Configure or ignore clock information.

cy_en_divider_types_t	dividerType
	Specifies which type of divider to use. More...

uint32_t	dividerNum
	Specifies which divider of the selected type to configure. More...

uint32_t	dividerIntValue
	The integer divider value. More...

uint32_t	dividerFracValue
	The fractional divider value if using a fractional clock. More...

Field Documentation

cy_en_divider_types_t cy_stc_ctdac_config_t::dividerType

Specifies which type of divider to use.

Can be integer or fractional divider. Not used if updateMode is CY_CTDAC_UPDATE_DIRECT_WRITE

uint32_t cy_stc_ctdac_config_t::dividerNum

Specifies which divider of the selected type to configure.

uint32_t cy_stc_ctdac_config_t::dividerIntValue

The integer divider value.

The divider value causes integer division of (divider value + 1). Not used if updateMode is CY_CTDAC_UPDATE_DIRECT_WRITE or CY_CTDAC_UPDATE_STROBE_EDGE_IMMEDIATE

uint32_t cy_stc_ctdac_config_t::dividerFracValue

The fractional divider value if using a fractional clock.