Functions

General Description

Functions
void	Cy_SysClk_ClkPwrSetDivider (uint32_t divider)
	Sets the clock divider for Power clock. More...
uint32_t	Cy_SysClk_ClkPwrGetDivider (void)
	Returns the clock divider of Power clock. More...
uint32_t	Cy_SysClk_ClkPwrGetFrequency (void)
	Reports the output clock signal frequency of Power clock. More...
void	Cy_SysClk_ClkPwrSetSource (cy_en_clkpwr_in_sources_t source)
	Sets the source for the Power clock. More...
cy_en_clkpwr_in_sources_t	Cy_SysClk_ClkPwrGetSource (void)
	Reports the source for the Power clock. More...

Function Documentation

Cy_SysClk_ClkPwrSetDivider()

void Cy_SysClk_ClkPwrSetDivider

(

uint32_t

divider

)

Sets the clock divider for Power clock.

Parameters

divider

divider value between 1 and 256.

Function Usage

    /* Scenario: Set CLKPWR divider to 8 */
    #if (defined (CY_IP_MXS40SSRSS) && (CY_MXS40SSRSS_VER_1_2 > 0UL))

    if(8UL != Cy_SysClk_ClkPwrGetDivider())
    {
        /* Set the CLKPWR divider to 8 */
        (void)Cy_SysClk_ClkPwrSetDivider(8UL);
    }

    /* Check the CLKPWR frequency */
    uint32_t freq = Cy_SysClk_ClkPwrGetFrequency();

Cy_SysClk_ClkPwrGetDivider()

uint32_t Cy_SysClk_ClkPwrGetDivider

(

void

)

Returns the clock divider of Power clock.

Returns

divider value in range 1..256.

Function Usage

    /* Scenario: Set CLKPWR divider to 8 */
    #if (defined (CY_IP_MXS40SSRSS) && (CY_MXS40SSRSS_VER_1_2 > 0UL))

    if(8UL != Cy_SysClk_ClkPwrGetDivider())
    {
        /* Set the CLKPWR divider to 8 */
        (void)Cy_SysClk_ClkPwrSetDivider(8UL);
    }

    /* Check the CLKPWR frequency */
    uint32_t freq = Cy_SysClk_ClkPwrGetFrequency();

Cy_SysClk_ClkPwrGetFrequency()

uint32_t Cy_SysClk_ClkPwrGetFrequency

(

void

)

Reports the output clock signal frequency of Power clock.

Returns

The frequency, in Hz.

Function Usage

    /* Scenario: Set CLKPWR divider to 8 */
    #if (defined (CY_IP_MXS40SSRSS) && (CY_MXS40SSRSS_VER_1_2 > 0UL))

    if(8UL != Cy_SysClk_ClkPwrGetDivider())
    {
        /* Set the CLKPWR divider to 8 */
        (void)Cy_SysClk_ClkPwrSetDivider(8UL);
    }

    /* Check the CLKPWR frequency */
    uint32_t freq = Cy_SysClk_ClkPwrGetFrequency();

Cy_SysClk_ClkPwrSetSource()

void Cy_SysClk_ClkPwrSetSource

(

cy_en_clkpwr_in_sources_t

source

)

Sets the source for the Power clock.

Parameters

source

cy_en_clkpwr_in_sources_t

Function Usage

    /* Scenario: CLKPWR source needs to be updated to the IMO. */
    #if (defined (CY_IP_MXS40SSRSS) && (CY_MXS40SSRSS_VER_1_2 > 0UL))

    if(CY_SYSCLK_CLKPWR_IN_IMO != Cy_SysClk_ClkPwrGetSource())
    {
        Cy_SysClk_ClkPwrSetSource(CY_SYSCLK_CLKPWR_IN_IMO);
    }
    #endif

Cy_SysClk_ClkPwrGetSource()

cy_en_clkpwr_in_sources_t Cy_SysClk_ClkPwrGetSource

(

void

)

Reports the source for the Power clock.

Returns

cy_en_clkpwr_in_sources_t

Function Usage

    /* Scenario: CLKPWR source needs to be updated to the IMO. */
    #if (defined (CY_IP_MXS40SSRSS) && (CY_MXS40SSRSS_VER_1_2 > 0UL))

    if(CY_SYSCLK_CLKPWR_IN_IMO != Cy_SysClk_ClkPwrGetSource())
    {
        Cy_SysClk_ClkPwrSetSource(CY_SYSCLK_CLKPWR_IN_IMO);
    }
    #endif