SysAnalog (System Analog Reference Block)

General Description

This driver provides an interface for configuring the Analog Reference (AREF), Low Power Oscillator (LpOsc), Deep Sleep Clock and Timer blocks and querying the INTR_CAUSE register of the Programmable Analog SubSystem (PASS) hardware block.

The functions and other declarations used in this driver are in cy_sysanalog.h. You can include cy_pdl.h to get access to all functions and declarations in the PDL.

PASS block structure

The Programmable Analog SubSystem (PASS) hardware block contains a set of analog subblocks such as AREF, CTB, SAR, analog routing switches and others. In order to provide a firmware interface to PASS, subblocks are united into groups, which have their own drivers: SysAnalog, CTB and SAR.

SysAnalog Features Description

SysAnalog driver includes the following features:

• AREF
• Low Power Oscillator (Available only for PASS_ver2.)
• Deep Sleep Clock (Available only for PASS_ver2.)
• Timer (Available only for PASS_ver2.)

The following sections describe how to initialize driver features:

• AREF Configuration
• Low Power Oscillator, Deep Sleep Clock and Timer Configuration

AREF

The AREF block has the following features:

• Generates a voltage reference (VREF) from one of three sources:
  • Local 1.2 V reference (low noise, optimized for analog performance)
  • Reference from the SRSS (high noise, not recommended for analog performance)
  • An external pin
• Generates a 1 uA "zero dependency to absolute temperature" (IZTAT) current reference that is independent of temperature variations. It can come from one of two sources:
  • Local reference (low noise, optimized for analog performance)
  • Reference from the SRSS (high noise, not recommended for analog performance)
• Generates a "proportional to absolute temperature" (IPTAT) current reference
• Option to enable local references in Deep Sleep mode

The locally generated references are the recommended sources for blocks in the PASS because they have tighter accuracy, temperature stability, and lower noise than the SRSS references. The SRSS references can be used to save power if the low accuracy and higher noise can be tolerated.

The outputs of the AREF are consumed by multiple blocks in the PASS and by the CapSense (CSDv2) block. In some cases, these blocks have the option of using the references from the AREF. This selection would be in the respective drivers for these blocks. In some cases, these blocks require the references from the AREF to function.

AREF Output	SAR	CTDAC	CTB	CSDv2
VREF	optional	optional	–	optional
IZTAT	required	–	optional	optional
IPTAT	–	–	required	–

This driver provides a function to query the INTR_CAUSE register of the PASS. There are two interrupts in the PASS:

1. one global interrupt for all CTBs (up to 4)
2. one global interrupt for all CTDACs (up to 4)

Because the interrupts are global, the INTR_CAUSE register is needed to query which hardware instance triggered the interrupt.

AREF Configuration

To configure the AREF, call Cy_SysAnalog_Init and provide a pointer to the configuration structure, cy_stc_sysanalog_config_t. Three predefined structures are provided in this driver to cover a majority of use cases:

• Cy_SysAnalog_Fast_Local (recommended for analog performance)
• Cy_SysAnalog_Fast_SRSS
• Cy_SysAnalog_Fast_External

After initialization, call Cy_SysAnalog_Enable to enable the hardware.

Deep Sleep Operation

The AREF current and voltage references can be enabled to operate in Deep Sleep mode with Cy_SysAnalog_SetDeepSleepMode. There are four options for Deep Sleep operation:

• CY_SYSANALOG_DEEPSLEEP_DISABLE : Disable AREF IP block
• CY_SYSANALOG_DEEPSLEEP_IPTAT_1 : Enable IPTAT generator for fast wakeup from Deep Sleep mode. IPTAT outputs for CTBs are disabled.
• CY_SYSANALOG_DEEPSLEEP_IPTAT_2 : Enable IPTAT generator and IPTAT outputs for CTB
• CY_SYSANALOG_DEEPSLEEP_IPTAT_IZTAT_VREF : Enable all generators and outputs: IPTAT, IZTAT, and VREF

Recall that the CTB requires the IPTAT reference. For the CTB to operate at the 1 uA current mode in Deep Sleep mode, the AREF must be enabled for CY_SYSANALOG_DEEPSLEEP_IPTAT_IZTAT_VREF. For the CTB to operate at the 100 nA current mode in Deep Sleep mode, the AREF must be enabled for CY_SYSANALOG_DEEPSLEEP_IPTAT_2 minimum. In this lower current mode, the AREF IPTAT must be redirected to the CTB IZTAT. See the high level function Cy_CTB_SetCurrentMode in the CTB PDL driver.

If the CTDAC is configured to use the VREF in Deep Sleep mode, the AREF must be enabled for CY_SYSANALOG_DEEPSLEEP_IPTAT_IZTAT_VREF.

Note

The SRSS references are not available to the AREF in Deep Sleep mode. When operating in Deep Sleep mode, the local or external references must be selected.

Low Power Oscillator

Features:

• Internal PASS_ver2 8MHz oscillator which does not require any external components.
• Can work in Deep Sleep power mode.
• Can be used as a clock source for the Deep Sleep Clock.

Low Power Oscillator clocking mode is configured by cy_stc_sysanalog_deep_sleep_config_t::lpOscDsMode configuration structure item, which should be passed as a parameter to Cy_SysAnalog_DeepSleepInit function. See Low Power Oscillator Functions for other Low Power Oscillator control functions.

Deep Sleep Clock

Features:

• Internal PASS_ver2 deep sleep capable clock selector/divider
• Can be used as clock source for CTB pump, SAR ADC and Timer

Deep Sleep clock is configurable by cy_stc_sysanalog_deep_sleep_config_t::dsClkSource and cy_stc_sysanalog_deep_sleep_config_t::dsClkdivider configuration structure items, which should be passed as a parameter to Cy_SysAnalog_DeepSleepInit function.

Timer

Features:

• Internal PASS_ver2 16-bit down counting timer
• Can be used to trigger one or few SAR ADCs
• Can be clocked from
  • Peripheral Clock (CLK_PERI),
  • Low Frequency Clock (CLK_LF)
  • Deep Sleep Clock
• If clocked from Deep Sleep Clock, timer can be used to trigger SAR ADC scans in Deep Sleep power mode.

Timer is configurable by cy_stc_sysanalog_deep_sleep_config_t::timerClock and cy_stc_sysanalog_deep_sleep_config_t::timerPeriod configuration structure items, which should be passed as a parameter to Cy_SysAnalog_DeepSleepInit function. Also see Timer Functions for other Timer configuration and control functions.

Low Power Oscillator, Deep Sleep Clock and Timer Configuration

To configure Low Power Oscillator, Deep Sleep Clock and Timer blocks, call Cy_SysAnalog_DeepSleepInit function and provide pointer to PASS block and pointer to the cy_stc_sysanalog_deep_sleep_config_t configuration structure. In order to start Low Power Oscillator and Timer, call corresponding enable functions:

    /* Initializes Deep Sleep features */
    const cy_stc_sysanalog_deep_sleep_config_t dsConfig =
    {
        /*.lpOscDsMode  */ CY_SYSANALOG_LPOSC_ALWAYS_ON,
        /*.dsClkSource  */ CY_SYSANALOG_DEEPSLEEP_SRC_LPOSC,
        /*.dsClkdivider */ CY_SYSANALOG_DEEPSLEEP_CLK_DIV_BY_4,
        /*.timerClock   */ CY_SYSANALOG_TIMER_CLK_DEEPSLEEP,
        /*.timerPeriod  */ 4000UL
    };
    
    if (CY_SYSANALOG_SUCCESS == Cy_SysAnalog_DeepSleepInit(PASS, &dsConfig))
    {
        /* Enable LpOsc and Timer blocks. */
        Cy_SysAnalog_LpOscEnable(PASS);
        Cy_SysAnalog_TimerEnable(PASS);
    }

More Information

For more information on the AREF, Deep Sleep Clock and Timer, refer to the technical reference manual (TRM).

Changelog

Version	Changes	Reason for Change
2.10	The CY_SYSANALOG_STARTUP_NORMAL and Cy_SysAnalog_SetArefMode are deprecated. The HW is anyways initialized with the CY_SYSANALOG_STARTUP_FAST.	User experience enhancement.
2.0	Added new features: LPOSC, DSCLK, TIMER.	New silicon family support.
1.10.1	Minor documentation updates.	Documentation enhancement.
1.10	Flattened the organization of the driver source code into the single source directory and the single include directory.	Driver library directory-structure simplification.
	Added register access layer. Use register access macros instead of direct register access using dereferenced pointers.	Makes register access device-independent, so that the PDL does not need to be recompiled for each supported part number.
1.0	Initial version

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