General Description

Functions
void	Cy_GPIO_SetAmuxSplit (cy_en_amux_split_t switchCtrl, cy_en_gpio_amuxconnect_t amuxConnect, cy_en_gpio_amuxselect_t amuxBus)
	Configure a specific AMux bus splitter switch cell into a specific configuration. More...

cy_en_gpio_amuxconnect_t	Cy_GPIO_GetAmuxSplit (cy_en_amux_split_t switchCtrl, cy_en_gpio_amuxselect_t amuxBus)
	Returns the configuration of a specific AMux bus splitter switch cell. More...

__STATIC_INLINE uint32_t	Cy_GPIO_Read (GPIO_PRT_Type *base, uint32_t pinNum)
	Reads the current logic level on the input buffer of the pin. More...

__STATIC_INLINE void	Cy_GPIO_Write (GPIO_PRT_Type *base, uint32_t pinNum, uint32_t value)
	Write a logic 0 or logic 1 state to the output driver. More...

__STATIC_INLINE uint32_t	Cy_GPIO_ReadOut (GPIO_PRT_Type *base, uint32_t pinNum)
	Reads the current logic level on the pin output driver. More...

__STATIC_INLINE void	Cy_GPIO_Set (GPIO_PRT_Type *base, uint32_t pinNum)
	Set a pin output to logic state high. More...

__STATIC_INLINE void	Cy_GPIO_Clr (GPIO_PRT_Type *base, uint32_t pinNum)
	Set a pin output to logic state Low. More...

__STATIC_FORCEINLINE void	Cy_GPIO_Inv (GPIO_PRT_Type *base, uint32_t pinNum)
	Set a pin output logic state to the inverse of the current output logic state. More...

__STATIC_INLINE void	Cy_GPIO_SetDrivemode (GPIO_PRT_Type *base, uint32_t pinNum, uint32_t value)
	Configures the pin output buffer drive mode and input buffer enable. More...

__STATIC_INLINE uint32_t	Cy_GPIO_GetDrivemode (GPIO_PRT_Type *base, uint32_t pinNum)
	Returns the pin output buffer drive mode and input buffer enable state. More...

__STATIC_INLINE void	Cy_GPIO_SetVtrip (GPIO_PRT_Type *base, uint32_t pinNum, uint32_t value)
	Configures the GPIO pin input buffer voltage threshold mode. More...

__STATIC_INLINE uint32_t	Cy_GPIO_GetVtrip (GPIO_PRT_Type *base, uint32_t pinNum)
	Returns the pin input buffer voltage threshold mode. More...

void	Cy_GPIO_SetVtripAuto (GPIO_PRT_Type *base, uint32_t pinNum, uint32_t value)
	Configures the GPIO pin input buffer for automotive compatible or not. More...

uint32_t	Cy_GPIO_GetVtripAuto (GPIO_PRT_Type *base, uint32_t pinNum)
	Returns the pin input buffer voltage whether it is automotive compatible or not. More...

__STATIC_INLINE void	Cy_GPIO_SetSlewRate (GPIO_PRT_Type *base, uint32_t pinNum, uint32_t value)
	Configures the pin output buffer slew rate. More...

__STATIC_INLINE uint32_t	Cy_GPIO_GetSlewRate (GPIO_PRT_Type *base, uint32_t pinNum)
	Returns the pin output buffer slew rate. More...

__STATIC_INLINE void	Cy_GPIO_SetDriveSel (GPIO_PRT_Type *base, uint32_t pinNum, uint32_t value)
	Configures the pin output buffer drive strength. More...

__STATIC_INLINE uint32_t	Cy_GPIO_GetDriveSel (GPIO_PRT_Type *base, uint32_t pinNum)
	Returns the pin output buffer drive strength. More...

__STATIC_INLINE void	Cy_GPIO_WritePort (GPIO_PRT_Type *base, uint32_t value)
	Write value to the whole GPIO port. More...

Function Documentation

◆ Cy_GPIO_SetAmuxSplit()

void Cy_GPIO_SetAmuxSplit	(	cy_en_amux_split_t	switchCtrl,
		cy_en_gpio_amuxconnect_t	amuxConnect,
		cy_en_gpio_amuxselect_t	amuxBus
	)

Configure a specific AMux bus splitter switch cell into a specific configuration.

Parameters

switchCtrl	Selects specific AMux bus splitter cell between two segments. The cy_en_amux_split_t enumeration can be found in the GPIO header file for the device package.
amuxConnect	Selects configuration of the three switches within the splitter cell
amuxBus	Selects which AMux bus within the splitter is being configured

Note: This API is available for the CAT1A and CAT1D devices.

◆ Cy_GPIO_GetAmuxSplit()

cy_en_gpio_amuxconnect_t Cy_GPIO_GetAmuxSplit	(	cy_en_amux_split_t	switchCtrl,
		cy_en_gpio_amuxselect_t	amuxBus
	)

Returns the configuration of a specific AMux bus splitter switch cell.

Parameters

switchCtrl	Selects specific AMux bus splitter cell between two segments. The cy_en_amux_split_t enumeration can be found in the GPIO header file for the device package.
amuxBus	Selects which AMux bus within the splitter is being configured

Returns: Returns configuration of the three switches in the selected splitter cell

Note: This API is available for the CAT1A and CAT1D devices.

◆ Cy_GPIO_Read()

__STATIC_INLINE uint32_t Cy_GPIO_Read	(	GPIO_PRT_Type *	base,
		uint32_t	pinNum
	)

Reads the current logic level on the input buffer of the pin.

Parameters

base	Pointer to the pin's port register base address
pinNum	Position of the pin bit-field within the port register. Bit position 8 is the routed pin through the port glitch filter.

Returns: Logic level present on the pin

Function Usage: /* Scenario: P0.3 was initialized and input buffer enabled */
/* Read the input state of P0.3 */
if(1UL == Cy_GPIO_Read(P0_3_PORT, P0_3_NUM))
{
/* Insert logic for High pin state */
}
else
{
/* Insert logic for Low pin state */
}

◆ Cy_GPIO_Write()

__STATIC_INLINE void Cy_GPIO_Write	(	GPIO_PRT_Type *	base,
		uint32_t	pinNum,
		uint32_t	value
	)

Write a logic 0 or logic 1 state to the output driver.

This function should be used only for software driven pins. It does not have any effect on peripheral driven pins.

Parameters

base	Pointer to the pin's port register base address
pinNum	Position of the pin bit-field within the port register
value	Logic level to drive out on the pin

Function Usage: uint32_t pinState = 0UL;
/* Control P0.3 based on the pinState variable */
Cy_GPIO_Write(P0_3_PORT, P0_3_NUM, pinState);

◆ Cy_GPIO_ReadOut()

__STATIC_INLINE uint32_t Cy_GPIO_ReadOut	(	GPIO_PRT_Type *	base,
		uint32_t	pinNum
	)

Reads the current logic level on the pin output driver.

Parameters

base	Pointer to the pin's port register base address
pinNum	Position of the pin bit-field within the port register

Returns: Logic level on the pin output driver

Function Usage: /* Write logic low to P0.3 */
Cy_GPIO_Write(P0_3_PORT, P0_3_NUM, 0UL);
/* Get the output value of P0.3 */
if(0UL != Cy_GPIO_ReadOut(P0_3_PORT, P0_3_NUM))
{
/* Insert error handling */
}

◆ Cy_GPIO_Set()

__STATIC_INLINE void Cy_GPIO_Set	(	GPIO_PRT_Type *	base,
		uint32_t	pinNum
	)

Set a pin output to logic state high.

This function should be used only for software driven pins. It does not have any effect on peripheral driven pins.

Parameters

base	Pointer to the pin's port register base address
pinNum	Position of the pin bit-field within the port register

Function Usage: /* Set P0.3 (out value = High) */
Cy_GPIO_Set(P0_3_PORT, P0_3_NUM);

◆ Cy_GPIO_Clr()

__STATIC_INLINE void Cy_GPIO_Clr	(	GPIO_PRT_Type *	base,
		uint32_t	pinNum
	)

Set a pin output to logic state Low.

This function should be used only for software driven pins. It does not have any effect on peripheral driven pins.

Parameters

base	Pointer to the pin's port register base address
pinNum	Position of the pin bit-field within the port register

Function Usage: /* Clear P0.3 (out value = Low) */
Cy_GPIO_Clr(P0_3_PORT, P0_3_NUM);

◆ Cy_GPIO_Inv()

__STATIC_FORCEINLINE void Cy_GPIO_Inv	(	GPIO_PRT_Type *	base,
		uint32_t	pinNum
	)

Set a pin output logic state to the inverse of the current output logic state.

This function should be used only for software driven pins. It does not have any effect on peripheral driven pins.

Parameters

base	Pointer to the pin's port register base address
pinNum	Position of the pin bit-field within the port register

Function Usage: /* Invert P0.3 (out value = ~(out value)) */
Cy_GPIO_Inv(P0_3_PORT, P0_3_NUM);

◆ Cy_GPIO_SetDrivemode()

__STATIC_INLINE void Cy_GPIO_SetDrivemode	(	GPIO_PRT_Type *	base,
		uint32_t	pinNum,
		uint32_t	value
	)

Configures the pin output buffer drive mode and input buffer enable.

The output buffer drive mode and input buffer enable are combined into a single parameter. The drive mode controls the behavior of the pin in general. Enabling the input buffer allows the digital pin state to be read but also contributes to extra current consumption.

Parameters

base	Pointer to the pin's port register base address
pinNum	Position of the pin bit-field within the port register
value	Pin drive mode. Options are detailed in Pin drive mode macros

Note: This function modifies a port register in a read-modify-write operation. It is not thread safe as the resource is shared among multiple pins on a port.

Function Usage: /* Scenario: Enter deep-sleep with reduced leakage current on P0.3 */
/* Get the drive mode of P0.3 */
if(CY_GPIO_DM_STRONG== Cy_GPIO_GetDrivemode(P0_3_PORT, P0_3_NUM))
{
/* Change the drive mode of P0.3 to analog (hi-z, input buffer off) */
Cy_GPIO_SetDrivemode(P0_3_PORT, P0_3_NUM, CY_GPIO_DM_ANALOG);
}

◆ Cy_GPIO_GetDrivemode()

__STATIC_INLINE uint32_t Cy_GPIO_GetDrivemode	(	GPIO_PRT_Type *	base,
		uint32_t	pinNum
	)

Returns the pin output buffer drive mode and input buffer enable state.

Parameters

base	Pointer to the pin's port register base address
pinNum	Position of the pin bit-field within the port register

Returns: Pin drive mode. Options are detailed in Pin drive mode macros

Function Usage: /* Scenario: Enter deep-sleep with reduced leakage current on P0.3 */
/* Get the drive mode of P0.3 */
if(CY_GPIO_DM_STRONG== Cy_GPIO_GetDrivemode(P0_3_PORT, P0_3_NUM))
{
/* Change the drive mode of P0.3 to analog (hi-z, input buffer off) */
Cy_GPIO_SetDrivemode(P0_3_PORT, P0_3_NUM, CY_GPIO_DM_ANALOG);
}

◆ Cy_GPIO_SetVtrip()

__STATIC_INLINE void Cy_GPIO_SetVtrip	(	GPIO_PRT_Type *	base,
		uint32_t	pinNum,
		uint32_t	value
	)

Configures the GPIO pin input buffer voltage threshold mode.

Parameters

base	Pointer to the pin's port register base address
pinNum	Position of the pin bit-field within the port register
value	Pin voltage threshold mode. Options are detailed in Voltage trip mode macros

Note: This function modifies a port register in a read-modify-write operation. It is not thread safe as the resource is shared among multiple pins on a port.

Function Usage: /* Scenario: Connect the pin to a TTL hardware */
/* Get the vtrip value of P0.3 */
if(CY_GPIO_VTRIP_CMOS == Cy_GPIO_GetVtrip(P0_3_PORT, P0_3_NUM))
{
/* Change the vtrip of P0.3 to LVTTL */
Cy_GPIO_SetVtrip(P0_3_PORT, P0_3_NUM, CY_GPIO_VTRIP_TTL);
}

◆ Cy_GPIO_GetVtrip()

__STATIC_INLINE uint32_t Cy_GPIO_GetVtrip	(	GPIO_PRT_Type *	base,
		uint32_t	pinNum
	)

Returns the pin input buffer voltage threshold mode.

Parameters

base	Pointer to the pin's port register base address
pinNum	Position of the pin bit-field within the port register

Returns: Pin voltage threshold mode. Options are detailed in Voltage trip mode macros

Function Usage: /* Scenario: Connect the pin to a TTL hardware */
/* Get the vtrip value of P0.3 */
if(CY_GPIO_VTRIP_CMOS == Cy_GPIO_GetVtrip(P0_3_PORT, P0_3_NUM))
{
/* Change the vtrip of P0.3 to LVTTL */
Cy_GPIO_SetVtrip(P0_3_PORT, P0_3_NUM, CY_GPIO_VTRIP_TTL);
}

◆ Cy_GPIO_SetVtripAuto()

void Cy_GPIO_SetVtripAuto	(	GPIO_PRT_Type *	base,
		uint32_t	pinNum,
		uint32_t	value
	)

Configures the GPIO pin input buffer for automotive compatible or not.

Parameters

base	Pointer to the pin's port register base address
pinNum	Position of the pin bit-field within the port register
value	Pin voltage threshold mode. Options are detailed in Voltage trip automotive compatible mode macros

Note: This function modifies a port register in a read-modify-write operation. It is not thread safe as the resource is shared among multiple pins on a port.; This API is available for CAT1B and CAT1C devices. TVIIBE also supports this functionality.

Function Usage: /* Scenario: Assume P0.3 is an SIO pin and that it is paired with P0.2.
Both pins are configured as input pins. The input signals
on P0.2 and P0.3 need to be interpreted as logic 0 or 1 at
0.5 x VDDIO threshold. */
/* Set the input buffer to be differential on the P0.2/P0.3 SIO pair */
Cy_GPIO_SetIbufMode(P0_3_PORT, P0_3_NUM, CY_SIO_IBUF_DIFFERENTIAL);
/* Choose VREF to be sourced from VDDIO (pin ref) */
Cy_GPIO_SetVrefSel(P0_3_PORT, P0_3_NUM, CY_SIO_VREF_PINREF);
/* Get the input buffer trip-point of P0.2/P0.3 pair */
if(CY_SIO_VTRIP_CMOS == Cy_GPIO_GetVtripSel(P0_3_PORT, P0_3_NUM))
{
/* Set the input buffer trip-point to 0.5 x VDDIO on the P0.2/P0.3 SIO pair */
Cy_GPIO_SetVtripSel(P0_3_PORT, P0_3_NUM, CY_SIO_VTRIP_0_5VDDIO_0_5VOH);
}

◆ Cy_GPIO_GetVtripAuto()

uint32_t Cy_GPIO_GetVtripAuto	(	GPIO_PRT_Type *	base,
		uint32_t	pinNum
	)

Returns the pin input buffer voltage whether it is automotive compatible or not.

Parameters

base	Pointer to the pin's port register base address
pinNum	Position of the pin bit-field within the port register

Returns: Pin voltage for automotive or not. Options are detailed in Voltage trip automotive compatible mode macros

Note: This API is available for CAT1B and CAT1C devices.

◆ Cy_GPIO_SetSlewRate()

__STATIC_INLINE void Cy_GPIO_SetSlewRate	(	GPIO_PRT_Type *	base,
		uint32_t	pinNum,
		uint32_t	value
	)

Configures the pin output buffer slew rate.

GPIO pins have fast and slow output slew rate options for the strong drivers configured using this API. By default the port works in fast slew mode. Slower slew rate results in reduced EMI and crosstalk and are recommended for low-frequency signals or signals without strict timing constraints.

Note: This function has no effect for the GPIO ports, where the slew rate configuration is not available. Refer to device datasheet for details.

Parameters

base	Pointer to the pin's port register base address
pinNum	Position of the pin bit-field within the port register
value	Pin slew rate. Options are detailed in Slew Rate Mode macros

Note: This function modifies a port register in a read-modify-write operation. It is not thread safe as the resource is shared among multiple pins on a port.

Function Usage: /* Scenario: Connect the pin to I2C (slow slew rate is preferred for low EMI) */
/* Get the slew rate value of P0.3 */
if(CY_GPIO_SLEW_FAST == Cy_GPIO_GetSlewRate(P0_3_PORT, P0_3_NUM))
{
/* Change the slew rate of P0.3 to Slow */
Cy_GPIO_SetSlewRate(P0_3_PORT, P0_3_NUM, CY_GPIO_SLEW_SLOW);
}

◆ Cy_GPIO_GetSlewRate()

__STATIC_INLINE uint32_t Cy_GPIO_GetSlewRate	(	GPIO_PRT_Type *	base,
		uint32_t	pinNum
	)

Returns the pin output buffer slew rate.

Parameters

base	Pointer to the pin's port register base address
pinNum	Position of the pin bit-field within the port register

Returns: Pin slew rate. Options are detailed in Slew Rate Mode macros

Function Usage: /* Scenario: Connect the pin to I2C (slow slew rate is preferred for low EMI) */
/* Get the slew rate value of P0.3 */
if(CY_GPIO_SLEW_FAST == Cy_GPIO_GetSlewRate(P0_3_PORT, P0_3_NUM))
{
/* Change the slew rate of P0.3 to Slow */
Cy_GPIO_SetSlewRate(P0_3_PORT, P0_3_NUM, CY_GPIO_SLEW_SLOW);
}

◆ Cy_GPIO_SetDriveSel()

__STATIC_INLINE void Cy_GPIO_SetDriveSel	(	GPIO_PRT_Type *	base,
		uint32_t	pinNum,
		uint32_t	value
	)

Configures the pin output buffer drive strength.

The drive strength field determines the active portion of the output drivers used and can affect the slew rate of output signals. Drive strength options are full drive strength (default), one-half strength, one-quarter strength, and oneeighth strength. Drive strength must be set to full drive strength when the slow slew rate bit (SLOW) is set.

Parameters

base	Pointer to the pin's port register base address
pinNum	Position of the pin bit-field within the port register.
value	Pin drive strength. Options are detailed in Pin drive strength macros

Note: This function modifies a port register in a read-modify-write operation. It is not thread safe as the resource is shared among multiple pins on a port.

Function Usage: /* Scenario: Reduce the drive current as part of power conservation strategy */
/* Get the drive current capability of P0.3 */
if(CY_GPIO_DRIVE_FULL == Cy_GPIO_GetDriveSel(P0_3_PORT, P0_3_NUM))
{
/* Change the drive current capability of P0.3 to 1/4 of full strength */
Cy_GPIO_SetDriveSel(P0_3_PORT, P0_3_NUM, CY_GPIO_DRIVE_1_4);
}

◆ Cy_GPIO_GetDriveSel()

__STATIC_INLINE uint32_t Cy_GPIO_GetDriveSel	(	GPIO_PRT_Type *	base,
		uint32_t	pinNum
	)

Returns the pin output buffer drive strength.

Parameters

base	Pointer to the pin's port register base address
pinNum	Position of the pin bit-field within the port register

Returns: Pin drive strength. Options are detailed in Pin drive strength macros

Function Usage: /* Scenario: Reduce the drive current as part of power conservation strategy */
/* Get the drive current capability of P0.3 */
if(CY_GPIO_DRIVE_FULL == Cy_GPIO_GetDriveSel(P0_3_PORT, P0_3_NUM))
{
/* Change the drive current capability of P0.3 to 1/4 of full strength */
Cy_GPIO_SetDriveSel(P0_3_PORT, P0_3_NUM, CY_GPIO_DRIVE_1_4);
}

◆ Cy_GPIO_WritePort()

__STATIC_INLINE void Cy_GPIO_WritePort	(	GPIO_PRT_Type *	base,
		uint32_t	value
	)

Write value to the whole GPIO port.

This function should be used only for software driven pins. It does not have any effect on peripheral driven pins.

Parameters

base	Pointer to the pin's port register base address
value	Logic level to drive out on the each pin of the selected port

Function Usage: uint32_t portState = 0x17UL;
/* Quickly initialize pins on P0
*
* Cy_GPIO_Pin_FastInit(P0_0_PORT, P0_0_NUM, CY_GPIO_DM_STRONG, 1UL, P0_0_GPIO);
* Cy_GPIO_Pin_FastInit(P0_1_PORT, P0_1_NUM, CY_GPIO_DM_STRONG, 1UL, P0_1_GPIO);
* Cy_GPIO_Pin_FastInit(P0_2_PORT, P0_3_NUM, CY_GPIO_DM_STRONG, 1UL, P0_2_GPIO);
* Cy_GPIO_Pin_FastInit(P0_3_PORT, P0_3_NUM, CY_GPIO_DM_STRONG, 1UL, P0_3_GPIO);
*
*/
/* Control P0 based on the portState variable
* In current case when only the first 4 pins were configured, the Cy_GPIO_WritePort function will guarantee
* that output values on P0.0 - P0.4 will have the same as in the portState variable.
* For example, if portState = 0x17 values on pins will be as expected ('0111'), but if P0.5 wasn't
* configured the value for this pin will not have any affect on the output.
*/
Cy_GPIO_WritePort(GPIO_PORT0, portState);

General Description

Functions

Function Documentation

◆ Cy_GPIO_SetAmuxSplit()

◆ Cy_GPIO_GetAmuxSplit()

◆ Cy_GPIO_Read()

◆ Cy_GPIO_Write()

◆ Cy_GPIO_ReadOut()

◆ Cy_GPIO_Set()

◆ Cy_GPIO_Clr()

◆ Cy_GPIO_Inv()

◆ Cy_GPIO_SetDrivemode()

◆ Cy_GPIO_GetDrivemode()

◆ Cy_GPIO_SetVtrip()

◆ Cy_GPIO_GetVtrip()

◆ Cy_GPIO_SetVtripAuto()

◆ Cy_GPIO_GetVtripAuto()

◆ Cy_GPIO_SetSlewRate()

◆ Cy_GPIO_GetSlewRate()

◆ Cy_GPIO_SetDriveSel()

◆ Cy_GPIO_GetDriveSel()

◆ Cy_GPIO_WritePort()