Enumerated Types

General Description

Enumerations
enum	cy_en_ctb_opamp_sel_t {   CY_CTB_OPAMP_NONE = 0UL,   CY_CTB_OPAMP_0 = CTBM_INTR_COMP0_Msk,   CY_CTB_OPAMP_1 = CTBM_INTR_COMP1_Msk,   CY_CTB_OPAMP_BOTH = CTBM_INTR_COMP0_Msk | CTBM_INTR_COMP1_Msk }
	Most functions allow you to configure a single opamp or both opamps at once. More...
enum	cy_en_ctb_deep_sleep_t {   CY_CTB_DEEPSLEEP_DISABLE = 0UL,   CY_CTB_DEEPSLEEP_ENABLE = CTBM_CTB_CTRL_DEEPSLEEP_ON_Msk }
	Enable or disable CTB while in Deep Sleep mode. More...
enum	cy_en_ctb_power_t {   CY_CTB_POWER_OFF = 0UL,   CY_CTB_POWER_LOW = 1UL,   CY_CTB_POWER_MEDIUM = 2UL,   CY_CTB_POWER_HIGH = 3UL,   CY_CTB_POWER_PS_LOW = 5UL,   CY_CTB_POWER_PS_MEDIUM = 6UL,   CY_CTB_POWER_PS_HIGH = 7UL }
	Configure the power mode of each opamp. More...
enum	cy_en_ctb_mode_t {   CY_CTB_MODE_OPAMP1X = 0UL,   CY_CTB_MODE_OPAMP10X = 1UL << CTBM_OA_RES0_CTRL_OA0_DRIVE_STR_SEL_Pos,   CY_CTB_MODE_COMP = 1UL << CTBM_OA_RES0_CTRL_OA0_COMP_EN_Pos }
	The output stage of each opamp can be configured for low-drive strength (1X) to drive internal circuits, for high-drive strength (10X) to drive external circuits, or as a comparator. More...
enum	cy_en_ctb_pump_t {   CY_CTB_PUMP_DISABLE = 0UL,   CY_CTB_PUMP_ENABLE = CTBM_OA_RES0_CTRL_OA0_PUMP_EN_Msk }
	Each opamp has a charge pump to increase the input range to the rails. More...
enum	cy_en_ctb_comp_edge_t {   CY_CTB_COMP_EDGE_DISABLE = 0UL,   CY_CTB_COMP_EDGE_RISING = 1UL << CTBM_OA_RES0_CTRL_OA0_COMPINT_Pos,   CY_CTB_COMP_EDGE_FALLING = 2UL << CTBM_OA_RES0_CTRL_OA0_COMPINT_Pos,   CY_CTB_COMP_EDGE_BOTH = 3UL << CTBM_OA_RES0_CTRL_OA0_COMPINT_Pos }
	Configure the type of edge that will trigger a comparator interrupt or disable the interrupt entirely. More...
enum	cy_en_ctb_comp_level_t {   CY_CTB_COMP_DSI_TRIGGER_OUT_PULSE = 0UL,   CY_CTB_COMP_DSI_TRIGGER_OUT_LEVEL = CTBM_OA_RES0_CTRL_OA0_DSI_LEVEL_Msk }
	Configure the comparator DSI trigger output level when output is synchronized. More...
enum	cy_en_ctb_comp_bypass_t {   CY_CTB_COMP_BYPASS_SYNC = 0UL,   CY_CTB_COMP_BYPASS_NO_SYNC = CTBM_OA_RES0_CTRL_OA0_BYPASS_DSI_SYNC_Msk }
	Bypass the comparator output synchronization for DSI trigger. More...
enum	cy_en_ctb_comp_hyst_t {   CY_CTB_COMP_HYST_DISABLE = 0UL,   CY_CTB_COMP_HYST_10MV = CTBM_OA_RES0_CTRL_OA0_HYST_EN_Msk }
	Disable or enable the 10 mV hysteresis for the comparator. More...
enum	cy_en_ctb_switch_state_t {   CY_CTB_SWITCH_OPEN = 0UL,   CY_CTB_SWITCH_CLOSE = 1UL }
	Switch state, either open or closed, to be used in Cy_CTB_SetAnalogSwitch. More...
enum	cy_en_ctb_switch_register_sel_t {   CY_CTB_SWITCH_OA0_SW = 0UL,   CY_CTB_SWITCH_OA1_SW = 1UL,   CY_CTB_SWITCH_CTD_SW = 2UL }
	The switch register to be used in Cy_CTB_SetAnalogSwitch. More...
enum	cy_en_ctb_oa0_switches_t {   CY_CTB_SW_OA0_POS_AMUXBUSA_MASK = CTBM_OA0_SW_OA0P_A00_Msk,   CY_CTB_SW_OA0_POS_PIN0_MASK = CTBM_OA0_SW_OA0P_A20_Msk,   CY_CTB_SW_OA0_POS_PIN6_MASK = CTBM_OA0_SW_OA0P_A30_Msk,   CY_CTB_SW_OA0_NEG_PIN1_MASK = CTBM_OA0_SW_OA0M_A11_Msk,   CY_CTB_SW_OA0_NEG_OUT_MASK = CTBM_OA0_SW_OA0M_A81_Msk,   CY_CTB_SW_OA0_OUT_SARBUS0_MASK = CTBM_OA0_SW_OA0O_D51_Msk,   CY_CTB_SW_OA0_OUT_SHORT_1X_10X_MASK = CTBM_OA0_SW_OA0O_D81_Msk }
	Switch masks for Opamp0 to be used in Cy_CTB_SetAnalogSwitch. More...
enum	cy_en_ctb_oa1_switches_t {   CY_CTB_SW_OA1_POS_AMUXBUSB_MASK = CTBM_OA1_SW_OA1P_A03_Msk,   CY_CTB_SW_OA1_POS_PIN5_MASK = CTBM_OA1_SW_OA1P_A13_Msk,   CY_CTB_SW_OA1_POS_PIN7_MASK = CTBM_OA1_SW_OA1P_A43_Msk,   CY_CTB_SW_OA1_POS_AREF_MASK = CTBM_OA1_SW_OA1P_A73_Msk,   CY_CTB_SW_OA1_NEG_PIN4_MASK = CTBM_OA1_SW_OA1M_A22_Msk,   CY_CTB_SW_OA1_NEG_OUT_MASK = CTBM_OA1_SW_OA1M_A82_Msk,   CY_CTB_SW_OA1_OUT_SARBUS0_MASK = CTBM_OA1_SW_OA1O_D52_Msk,   CY_CTB_SW_OA1_OUT_SARBUS1_MASK = CTBM_OA1_SW_OA1O_D62_Msk,   CY_CTB_SW_OA1_OUT_SHORT_1X_10X_MASK = CTBM_OA1_SW_OA1O_D82_Msk }
	Switch masks for Opamp1 to be used in Cy_CTB_SetAnalogSwitch. More...
enum	cy_en_ctb_ctd_switches_t {   CY_CTB_SW_CTD_REF_OA1_OUT_MASK = CTBM_CTD_SW_CTDD_CRD_Msk,   CY_CTB_SW_CTD_REFSENSE_OA1_NEG_MASK = CTBM_CTD_SW_CTDS_CRS_Msk,   CY_CTB_SW_CTD_OUT_OA1_NEG_MASK = CTBM_CTD_SW_CTDS_COR_Msk,   CY_CTB_SW_CTD_OUT_PIN6_MASK = CTBM_CTD_SW_CTDO_C6H_Msk,   CY_CTB_SW_CTD_OUT_CHOLD_MASK = CTBM_CTD_SW_CTDO_COS_Msk,   CY_CTB_SW_CTD_OUT_OA0_1X_OUT_MASK = CTBM_CTD_SW_CTDH_COB_Msk,   CY_CTB_SW_CTD_CHOLD_CONNECT_MASK = CTBM_CTD_SW_CTDH_CHD_Msk,   CY_CTB_SW_CTD_CHOLD_OA0_POS_MASK = CTBM_CTD_SW_CTDH_CA0_Msk,   CY_CTB_SW_CTD_CHOLD_OA0_POS_ISOLATE_MASK = CTBM_CTD_SW_CTDH_CIS_Msk,   CY_CTB_SW_CTD_CHOLD_LEAKAGE_REDUCTION_MASK = CTBM_CTD_SW_CTDH_ILR_Msk }
	Switch masks for CTDAC to CTB routing to be used in Cy_CTB_SetAnalogSwitch. More...
enum	cy_en_ctb_switch_sar_seq_t {   CY_CTB_SW_SEQ_CTRL_D51_MASK = CTBM_CTB_SW_SQ_CTRL_P2_SQ_CTRL23_Msk,   CY_CTB_SW_SEQ_CTRL_D52_D62_MASK = CTBM_CTB_SW_SQ_CTRL_P3_SQ_CTRL23_Msk,   CY_CTB_SW_SEQ_CTRL_D51_D52_D62_MASK = CTBM_CTB_SW_SQ_CTRL_P2_SQ_CTRL23_Msk | CTBM_CTB_SW_SQ_CTRL_P3_SQ_CTRL23_Msk }
	Masks for CTB switches that can be controlled by the SAR sequencer. More...
enum	cy_en_ctb_compensation_cap_t {   CY_CTB_OPAMP_COMPENSATION_CAP_OFF = 0UL,   CY_CTB_OPAMP_COMPENSATION_CAP_MIN = 1UL,   CY_CTB_OPAMP_COMPENSATION_CAP_MED = 2UL,   CY_CTB_OPAMP_COMPENSATION_CAP_MAX = 3UL }
	Each opamp also has a programmable compensation capacitor block, that optimizes the stability of the opamp performance based on output load. More...
enum	cy_en_ctb_boost_en_t {   CY_CTB_OPAMP_BOOST_DISABLE = 0UL,   CY_CTB_OPAMP_BOOST_ENABLE = CTBM_OA_RES0_CTRL_OA0_BOOST_EN_Msk }
	Enable or disable the gain booster. More...
enum	cy_en_ctb_sample_hold_mode_t {   CY_CTB_SH_DISABLE = 0UL,   CY_CTB_SH_PREPARE_SAMPLE = 1UL,   CY_CTB_SH_SAMPLE = 2UL,   CY_CTB_SH_PREPARE_HOLD = 3UL,   CY_CTB_SH_HOLD = 4UL }
	Sample and hold modes for firmware sampling of the CTDAC output. More...
enum	cy_en_ctb_iptat_t {   CY_CTB_IPTAT_NORMAL = 0UL,   CY_CTB_IPTAT_LOW = 1UL << PASS_AREF_AREF_CTRL_CTB_IPTAT_SCALE_Pos }
	AREF IPTAT bias current output for the CTB. More...
enum	cy_en_ctb_clk_pump_source_t {   CY_CTB_CLK_PUMP_SRSS = 0UL,   CY_CTB_CLK_PUMP_PERI = 1UL << PASS_AREF_AREF_CTRL_CLOCK_PUMP_PERI_SEL_Pos,   CY_CTB_CLK_PUMP_DEEPSLEEP = 1UL }
	CTB charge pump clock sources. More...
enum	cy_en_ctb_current_mode_t {   CY_CTB_CURRENT_HIGH_ACTIVE = 0UL,   CY_CTB_CURRENT_HIGH_ACTIVE_DEEPSLEEP = 1UL,   CY_CTB_CURRENT_LOW_ACTIVE_DEEPSLEEP = 2UL }
	High level opamp current modes. More...
enum	cy_en_ctb_status_t {   CY_CTB_SUCCESS = 0x00UL,   CY_CTB_BAD_PARAM = CY_CTB_ID | CY_PDL_STATUS_ERROR | 0x01UL }
	Return states for Cy_CTB_Init, Cy_CTB_OpampInit, Cy_CTB_DeInit, and Cy_CTB_FastInit. More...

Enumeration Type Documentation

cy_en_ctb_opamp_sel_t

enum cy_en_ctb_opamp_sel_t

Most functions allow you to configure a single opamp or both opamps at once.

The Cy_CTB_SetInterruptMask function can be called with CY_CTB_OPAMP_NONE and interrupts will be disabled.

Enumerator
CY_CTB_OPAMP_NONE	For disabling interrupts for both opamps. Used with Cy_CTB_SetInterruptMask
CY_CTB_OPAMP_0	For configuring Opamp0.
CY_CTB_OPAMP_1	For configuring Opamp1.
CY_CTB_OPAMP_BOTH	For configuring both Opamp0 and Opamp1.

cy_en_ctb_deep_sleep_t

enum cy_en_ctb_deep_sleep_t

Enable or disable CTB while in Deep Sleep mode.

Enumerator
CY_CTB_DEEPSLEEP_DISABLE	CTB is disabled during Deep Sleep power mode.
CY_CTB_DEEPSLEEP_ENABLE	CTB remains enabled during Deep Sleep power mode.

cy_en_ctb_power_t

enum cy_en_ctb_power_t

Configure the power mode of each opamp.

Each power setting consumes different levels of current and supports a different input range and gain bandwidth.

Opamp Power	IDD	Gain bandwidth
OFF	0	NA
LOW	350 uA	1 MHz
MEDIUM	600 uA	3 MHz for 1X, 2.5 MHz for 10x
HIGH	1.5 mA	8 MHz for 1X, 6 MHz for 10x

Enumerator
CY_CTB_POWER_OFF	Opamp is off.
CY_CTB_POWER_LOW	Low power: IDD = 350 uA, GBW = 1 MHz for both 1x and 10x.
CY_CTB_POWER_MEDIUM	Medium power: IDD = 600 uA, GBW = 3 MHz for 1x and 2.5 MHz for 10x.
CY_CTB_POWER_HIGH	High power: IDD = 1500 uA, GBW = 8 MHz for 1x and 6 MHz for 10x.
CY_CTB_POWER_PS_LOW	Power Saver Low power mode: IDD = ~20uA with 1uA bias from AREF, GBW = ~100kHz for 1x/10x, offset correcting IDAC is disabled.
CY_CTB_POWER_PS_MEDIUM	Power Saver Medium power mode: IDD = ~40uA with 1uA bias from AREF, GBW = ~100kHz for 1x/10x, offset correcting IDAC is enabled.
CY_CTB_POWER_PS_HIGH	Power Saver High power mode: IDD = ~60uA with 1uA bias from AREF, GBW = ~200kHz for 1x/10x, offset correcting IDAC is enabled.

cy_en_ctb_mode_t

enum cy_en_ctb_mode_t

The output stage of each opamp can be configured for low-drive strength (1X) to drive internal circuits, for high-drive strength (10X) to drive external circuits, or as a comparator.

Enumerator
CY_CTB_MODE_OPAMP1X	Configure opamp for low drive strength for internal connections (1x)
CY_CTB_MODE_OPAMP10X	Configure opamp high drive strength for driving a device pin (10x)
CY_CTB_MODE_COMP	Configure opamp as a comparator.

cy_en_ctb_pump_t

enum cy_en_ctb_pump_t

Each opamp has a charge pump to increase the input range to the rails.

When the charge pump is enabled, the input range is 0 to VDDA. When disabled, the input range is 0 to VDDA - 1.5 V.

Charge Pump	Input Range (V)
OFF	0 to VDDA-1.5
ON	0 to VDDA

Note that in Deep Sleep mode, the charge pump is disabled so the input range is reduced.

Enumerator
CY_CTB_PUMP_DISABLE	Charge pump is disabled for an input range of 0 to VDDA - 1.5 V.
CY_CTB_PUMP_ENABLE	Charge pump is enabled for an input range of 0 to VDDA.

cy_en_ctb_comp_edge_t

enum cy_en_ctb_comp_edge_t

Configure the type of edge that will trigger a comparator interrupt or disable the interrupt entirely.

Enumerator
CY_CTB_COMP_EDGE_DISABLE	Disabled, no interrupts generated.
CY_CTB_COMP_EDGE_RISING	Rising edge generates an interrupt.
CY_CTB_COMP_EDGE_FALLING	Falling edge generates an interrupt.
CY_CTB_COMP_EDGE_BOTH	Both edges generate an interrupt.

cy_en_ctb_comp_level_t

enum cy_en_ctb_comp_level_t

Configure the comparator DSI trigger output level when output is synchronized.

Enumerator
CY_CTB_COMP_DSI_TRIGGER_OUT_PULSE	Send pulse on DSI for each edge of comparator output.
CY_CTB_COMP_DSI_TRIGGER_OUT_LEVEL	DSI output is synchronized version of comparator output.

cy_en_ctb_comp_bypass_t

enum cy_en_ctb_comp_bypass_t

Bypass the comparator output synchronization for DSI trigger.

Enumerator
CY_CTB_COMP_BYPASS_SYNC	Comparator output is synchronized for DSI trigger.
CY_CTB_COMP_BYPASS_NO_SYNC	Comparator output is not synchronized for DSI trigger.

cy_en_ctb_comp_hyst_t

enum cy_en_ctb_comp_hyst_t

Disable or enable the 10 mV hysteresis for the comparator.

Enumerator
CY_CTB_COMP_HYST_DISABLE	Disable hysteresis.
CY_CTB_COMP_HYST_10MV	Enable the 10 mV hysteresis.

cy_en_ctb_switch_state_t

enum cy_en_ctb_switch_state_t

Switch state, either open or closed, to be used in Cy_CTB_SetAnalogSwitch.

Enumerator
CY_CTB_SWITCH_OPEN	Open the switch.
CY_CTB_SWITCH_CLOSE	Close the switch.

cy_en_ctb_switch_register_sel_t

enum cy_en_ctb_switch_register_sel_t

The switch register to be used in Cy_CTB_SetAnalogSwitch.

The CTB has three registers for configuring the switch routing matrix.

Enumerator
CY_CTB_SWITCH_OA0_SW	Switch register for Opamp0.
CY_CTB_SWITCH_OA1_SW	Switch register for Opamp1.
CY_CTB_SWITCH_CTD_SW	Switch register for CTDAC routing.

cy_en_ctb_oa0_switches_t

enum cy_en_ctb_oa0_switches_t

Switch masks for Opamp0 to be used in Cy_CTB_SetAnalogSwitch.

Enumerator
CY_CTB_SW_OA0_POS_AMUXBUSA_MASK	Switch A00: Opamp0 non-inverting input to AMUXBUS A.
CY_CTB_SW_OA0_POS_PIN0_MASK	Switch A20: Opamp0 non-inverting input to Pin 0 of CTB device port.
CY_CTB_SW_OA0_POS_PIN6_MASK	Switch A30: Opamp0 non-inverting input to Pin 6 of CTB device port.
CY_CTB_SW_OA0_NEG_PIN1_MASK	Switch A11: Opamp0 inverting input to Pin 1 of CTB device port.
CY_CTB_SW_OA0_NEG_OUT_MASK	Switch A81: Opamp0 inverting input to Opamp0 output.
CY_CTB_SW_OA0_OUT_SARBUS0_MASK	Switch D51: Opamp0 output to sarbus0.
CY_CTB_SW_OA0_OUT_SHORT_1X_10X_MASK	Switch D81: Short Opamp0 1x with 10x outputs.

cy_en_ctb_oa1_switches_t

enum cy_en_ctb_oa1_switches_t

Switch masks for Opamp1 to be used in Cy_CTB_SetAnalogSwitch.

Enumerator
CY_CTB_SW_OA1_POS_AMUXBUSB_MASK	Switch A03: Opamp1 non-inverting input to AMUXBUS B.
CY_CTB_SW_OA1_POS_PIN5_MASK	Switch A13: Opamp1 non-inverting input to Pin 5 of CTB device port.
CY_CTB_SW_OA1_POS_PIN7_MASK	Switch A43: Opamp1 non-inverting input to Pin 7 of CTB device port.
CY_CTB_SW_OA1_POS_AREF_MASK	Switch A73: Opamp1 non-inverting input to device Analog Reference (AREF)
CY_CTB_SW_OA1_NEG_PIN4_MASK	Switch A22: Opamp1 inverting input to Pin 4 of CTB device port.
CY_CTB_SW_OA1_NEG_OUT_MASK	switch A82: Opamp1 inverting input to Opamp1 output
CY_CTB_SW_OA1_OUT_SARBUS0_MASK	Switch D52: Opamp1 output to sarbus0.
CY_CTB_SW_OA1_OUT_SARBUS1_MASK	Switch D62: Opamp1 output to sarbus1.
CY_CTB_SW_OA1_OUT_SHORT_1X_10X_MASK	Switch D82: Short Opamp1 1x with 10x outputs.

cy_en_ctb_ctd_switches_t

enum cy_en_ctb_ctd_switches_t

Switch masks for CTDAC to CTB routing to be used in Cy_CTB_SetAnalogSwitch.

Enumerator
CY_CTB_SW_CTD_REF_OA1_OUT_MASK	Switch CRD: Opamp1 output to CTDAC reference.
CY_CTB_SW_CTD_REFSENSE_OA1_NEG_MASK	Switch CRS: CTDAC reference sense to Opamp1 inverting input.
CY_CTB_SW_CTD_OUT_OA1_NEG_MASK	Switch COR: CTDAC output to Opamp1 inverting input.
CY_CTB_SW_CTD_OUT_PIN6_MASK	Switch C6H: CTDAC output to P6 of CTB device port.
CY_CTB_SW_CTD_OUT_CHOLD_MASK	Switch COS: CTDAC output to hold cap (deglitch capable).
CY_CTB_SW_CTD_OUT_OA0_1X_OUT_MASK	Switch COB: Drive CTDAC output with opamp0 1x output during hold mode.
CY_CTB_SW_CTD_CHOLD_CONNECT_MASK	Switch CHD: Hold cap connection.
CY_CTB_SW_CTD_CHOLD_OA0_POS_MASK	Switch CA0: Hold cap to Opamp0 non-inverting input.
CY_CTB_SW_CTD_CHOLD_OA0_POS_ISOLATE_MASK	Switch CIS: Opamp0 non-inverting input isolation (for hold cap)
CY_CTB_SW_CTD_CHOLD_LEAKAGE_REDUCTION_MASK	Switch ILR: Hold cap leakage reduction (drives far side of isolation switch CIS)

cy_en_ctb_switch_sar_seq_t

enum cy_en_ctb_switch_sar_seq_t

Masks for CTB switches that can be controlled by the SAR sequencer.

These masks are used in Cy_CTB_EnableSarSeqCtrl and Cy_CTB_DisableSarSeqCtrl.

The SAR ADC subsystem supports analog routes through three CTB switches on SARBUS0 and SARBUS1. This control allows for pins on the CTB dedicated port to route to the SAR ADC input channels:

• D51: Connects the inverting terminal of OA0 to SARBUS0
• D52: Connects the inverting terminal of OA1 to SARBUS0
• D62: Connects the inverting terminal of OA1 to SARBUS1

Enumerator
CY_CTB_SW_SEQ_CTRL_D51_MASK	Enable SAR sequencer control of the D51 switch.
CY_CTB_SW_SEQ_CTRL_D52_D62_MASK	Enable SAR sequencer control of the D52 and D62 switches.
CY_CTB_SW_SEQ_CTRL_D51_D52_D62_MASK	Enable SAR sequencer control of all three switches.

cy_en_ctb_compensation_cap_t

enum cy_en_ctb_compensation_cap_t

Each opamp also has a programmable compensation capacitor block, that optimizes the stability of the opamp performance based on output load.

The compensation cap will be set by the driver based on the opamp drive strength (1x or 10x) selection.

Enumerator
CY_CTB_OPAMP_COMPENSATION_CAP_OFF	No compensation.
CY_CTB_OPAMP_COMPENSATION_CAP_MIN	Minimum compensation - for 1x drive.
CY_CTB_OPAMP_COMPENSATION_CAP_MED	Medium compensation.
CY_CTB_OPAMP_COMPENSATION_CAP_MAX	Maximum compensation - for 10x drive.

cy_en_ctb_boost_en_t

enum cy_en_ctb_boost_en_t

Enable or disable the gain booster.

The gain booster will be set by the driver based on the opamp drive strength (1x or 10x) selection.

Enumerator
CY_CTB_OPAMP_BOOST_DISABLE	Disable gain booster - for 10x drive.
CY_CTB_OPAMP_BOOST_ENABLE	Enable gain booster - for 1x drive.

cy_en_ctb_sample_hold_mode_t

enum cy_en_ctb_sample_hold_mode_t

Sample and hold modes for firmware sampling of the CTDAC output.

To perform a sample or a hold, a preparation step must first be executed to open the required switches.

1. Call Cy_CTB_DACSampleAndHold with CY_CTB_SH_PREPARE_SAMPLE or CY_CTB_SH_PREPARE_HOLD
2. Enable or disable CTDAC output
3. Call Cy_CTB_DACSampleAndHold with CY_CTB_SH_SAMPLE or CY_CTB_SH_HOLD

Enumerator
CY_CTB_SH_DISABLE	The hold capacitor is not connected - this disables sample and hold.
CY_CTB_SH_PREPARE_SAMPLE	Prepares the required switches for a following sample.
CY_CTB_SH_SAMPLE	Performs a sample of the voltage.
CY_CTB_SH_PREPARE_HOLD	Prepares the required switches for a following hold.
CY_CTB_SH_HOLD	Performs a hold of the previously sampled voltage.

cy_en_ctb_iptat_t

enum cy_en_ctb_iptat_t

AREF IPTAT bias current output for the CTB.

The CTB bias current can be 1 uA (normal) or 100 nA (low current).

Enumerator
CY_CTB_IPTAT_NORMAL	1 uA bias current to the CTB
CY_CTB_IPTAT_LOW	100 nA bias current to the CTB

cy_en_ctb_clk_pump_source_t

enum cy_en_ctb_clk_pump_source_t

CTB charge pump clock sources.

The CTB pump clock can come from:

• a dedicated divider clock in the SRSS
• one of the CLK_PERI dividers

Enumerator
CY_CTB_CLK_PUMP_SRSS	Use the dedicated pump clock from SRSSp.
CY_CTB_CLK_PUMP_PERI	Use one of the CLK_PERI dividers.
CY_CTB_CLK_PUMP_DEEPSLEEP	Use the Deep Sleep Clock (Deep Sleep Clock) - applicable for PASS_v2 only.

cy_en_ctb_current_mode_t

enum cy_en_ctb_current_mode_t

High level opamp current modes.

Enumerator
CY_CTB_CURRENT_HIGH_ACTIVE	Uses 1 uA reference current with charge pump enabled. Available in Active and Low Power
CY_CTB_CURRENT_HIGH_ACTIVE_DEEPSLEEP	Uses 1 uA reference current with charge pump disabled. Available in all power modes
CY_CTB_CURRENT_LOW_ACTIVE_DEEPSLEEP	Uses 100 nA reference current with charge pump disabled. Available in all power modes

cy_en_ctb_status_t

enum cy_en_ctb_status_t

Return states for Cy_CTB_Init, Cy_CTB_OpampInit, Cy_CTB_DeInit, and Cy_CTB_FastInit.

Enumerator
CY_CTB_SUCCESS	Initialization completed successfully.
CY_CTB_BAD_PARAM	Input pointers were NULL and initialization could not be completed.